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參數(shù)資料
| 型號： | 84C300A |
| 英文描述： | 84C300A 4-Port Fast Ethernet Controller manual 3/98 |
| 中文描述： | 84C300A 4端口快速以太網(wǎng)控制器手冊3 / 98 |
| 文件頁數(shù)： | 4/56頁 |
| 文件大?。?/td> | 523K |
| 代理商： | 84C300A |
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84C300A 4-Port
Fast Ethernet Controller
4-4
MD400152/E
Pin
Pin Name
I/O
Description
Receive and Transmit FIFO Interface
31
RXINTEN
I
Receive Interface Enable
This is an active low input that acts as a chip enable to enable the receiver interface.
Driving this pin active enables the output drivers for the RXDC[1:4] and RXRDY[1:4],
pins. Also, this pin must be driven active before receive FIFO reads can be
performed.
32
TXINTEN
I
Transmit Interface Enable
This is an active low input that acts as a chip enable to enable the transmitter
interface. Driving this pin active enables the output drivers for the TXRET[1:4],
TXRDY[1:4] pins. Also, this pin must be driven active before transmit FIFO writes
can be and performed.
36
RXRDEN
I
Receive Read Enable
This is an active low input that, when driven active with the RXINTEN pin, enables
read operations from one of the four receive FIFOs within the chip.
37
TXWREN
I
Transmit Write Enable
This is an active low input that, when driven active with the TXINTEN pin, enables
write operations to one of the four transmit FIFOs within the chip.
35
RXRD_TXWR
I
Receive Read Transmit Write Clock
This clock input is also the chip’s read/write strobe to the chip’s eight
receive/transmit FIFOs. With the TXINTEN and TXWREN inputs active low,
this input becomes the write strobe for writing transmit data to one of the chip’s
transmit FIFOs. Similarly, with the RXINTEN and RXRDEN inputs active low, this
input becomes the read strobe for reading receive data from one of the chip’s receive
FIFOs. This input must be connected to a continuous clock whose maximum
frequency can be 33 MHz.
30, 29
RXTXPS[1:0]
I
Port Select
These inputs are used to select and identify which port will be accessed for the
following operations.
1. Receive FIFO Reads
2. Transmit FIFO Writes
3. Clearing a TXRET Condition
4. Clearing a RXDC Condition
5. Aborting a Receive Packet
RXTXPS[1:0]
RXTXPS1
RXTXPS0
Selected
Port
Port 1
Port 2
Port 3
Port 4
0
0
1
1
0
1
0
1
23, 24
25, 26
RXTXBE[3:0]
I
Receive Transmit Byte Enable
These are active low inputs that determine which bytes of the double
word for a receive FIFO read are driven with valid data or which bytes of a double
word being written to a transmit FIFO contain valid data.
Pin Description (cont.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 84C30A | 84C30A 10 Mbps Controller (MAC) manual 12/96 |
| 84C300A | 4-Port Fast Ethernet Controller(四端口快速以太網(wǎng)控制器) |
| 84CNQ035 | Schottky Rectifier |
| 84CNQ040 | Schottky Rectifier |
| 84CNQ045 | Schottky Rectifier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 84C30A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:84C30A 10 Mbps Controller (MAC) manual 12/96 |
| 84C3A-A12-J06 | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J06L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J08L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J10L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
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