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參數(shù)資料
| 型號： | 84C300A |
| 英文描述： | 84C300A 4-Port Fast Ethernet Controller manual 3/98 |
| 中文描述： | 84C300A 4端口快速以太網(wǎng)控制器手冊3 / 98 |
| 文件頁數(shù)： | 30/56頁 |
| 文件大小： | 523K |
| 代理商： | 84C300A |
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84C300A 4-Port
Fast Ethernet Controller
4-30
MD400152/E
programmed in the station address register that the
packet will not be rejected due to incorrect address
even its last 4 bits did not match.
Mode B: Transmit Packet Autopad Mode
This feature automatically pads packets to be trans-
mitted with ess han 60 bytes of data out o a minimum
IEEE 802.3 standard packet length of 60 bytes ex-
cluding FCS. Padding is done with bytes of 00 hex in
10 Mbit/sec Serial Mode and 55 hex in MII mode.
Mode C: Transmit No Preamble Mode
This mode prevents the transmitter from adding a
preamble pattern at the beginning of data to be
transmitted.
Mode E: Transmit No CRC Mode
This mode prevents a port’s transmitter from append-
ing transmit data with an FCS.
Mode G: Receive CRC Mode
In this mode a ports receiver oads the 4 bytes of FCS
into the receive FIFO along with the data allowing the
FCS value to be read out.
Mode H: Disable Receive Interrupts
With this bit set a ports receiver is disabled from
producing receive interrupts.
Full Duplex/Half Duplex Modes
Operation with Receive Own Transmit Disable. TABLE A
The following description assumes that a transceiver
is connected to the MAC.
Bit 3
Bit 5
‘OR’ FDUPLX
Pin*
0
(Default)
Mode
Functional Description
1
Half
Duplex
In this mode the transmit data looped back from the transceiver is ignored
by the controller. The data does not get written into the receive FIFO and
the Rxrdy does not reflect the incoming data.
In this mode the transceiver (In Full Duplex mode) will not loopback the
transmitted data. However, since data reception is possible during
transmission, bit 3 should be written with ‘0’ so that the data gets written
to the Receive FIFO.
In normal Half Duplex operation the PHY loops back the transmitted data
back to the MAC. In other words, the PHY always loops back the
transmitted data in half duplex mode. As far as the controller is concerned,
it knows that the data coming back is it’s own transmitted packet and since
bit 3 is not set, the transmitted packet gets written into the receive FIFO.
Reserved
0
(Default)
1
Full
Duplex
0
(Default)
0
(Default)
Loopback
Mode
1
1
Note:
There is no internal loopback within the MAC. Loopback is dependent on a PHY
connected to the MAC.
* The software bit setting and the hardware setting (pin #123, 124, 125 or 127) have an OR
relationship. This means that either the hardware or software setting will enable Full Duplex.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 84C30A | 84C30A 10 Mbps Controller (MAC) manual 12/96 |
| 84C300A | 4-Port Fast Ethernet Controller(四端口快速以太網(wǎng)控制器) |
| 84CNQ035 | Schottky Rectifier |
| 84CNQ040 | Schottky Rectifier |
| 84CNQ045 | Schottky Rectifier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 84C30A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:84C30A 10 Mbps Controller (MAC) manual 12/96 |
| 84C3A-A12-J06 | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J06L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J08L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J10L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
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