參數(shù)資料
型號： 84C300A
英文描述： 84C300A 4-Port Fast Ethernet Controller manual 3/98
中文描述： 84C300A 4端口快速以太網(wǎng)控制器手冊3 / 98
文件頁數(shù)： 14/56頁
文件大小： 523K
代理商： 84C300A
84C300A 4-Port
Fast Ethernet Controller
4-14
MD400152/E
3.0 Functional Description
On an Ethernet communication network, information is
transmitted and received in packets or frames. An Eth-
ernet frame consists of a preamble, two address fields, a
byte-count field, a data field and a frame check sequence
(FCS). Each field has a specific format which s described
in detail below. An Ethernet frame has a minimum length
of 64 bytes and a maximum ength of 1518 bytes exclusive
of he preamble. The Ethernet rame ormat s shown n he
figure below.
3.1 FRAME FORMAT
2.0 Introduction
The 84C300A is a 4-Port Ethernet Media Access Control-
ler (MAC) with a rich set of operating modes and features.
It is manufactured as a single-chip VLSI device to simplify
and enhance the development of multi-port Ethernet em-
bedded systems such as bridges, switches, and routers.
Two input/output paths are provided for interfacing to
physical layer devices. In IEEE-standard MII mode, the
84C300A provides an ndustry standard nterface support-
ing both 10Mbit/sec and 100Mbit/sec data rates. This
interface will directly connect with physical layer devices
such as SEEQ’s 80C240 100Base-T4 PHY without addi-
tional glue logic. In Serial mode, the chip supports the
standard Ethernet CSMA/CD protocol via a serial nterface
for transmit and receive data. All ports, in all interface
modes, support both Half and Full Duplex operation.
Each port of the 84C300A is feature compatible with
SEEQ’s 80C300 Ethernet Media Access Controller.
These features include: 64 bit Multicast filter, Transmit no
CRC, Transmit no Preamble, Transmit Packet
Autopadding, Receive CRC, Receive Own Transmit Dis-
able, Receive Group Address Mode, Fast Receive Dis-
card Mode, and Full Duplex Mode. Additionally, each port
supports: programmable defer time between transmit
packets, appending value of FCS on a packet-by-packet
basis, and pin-controllable per-port receive packet abort.
A high-bandwidth universal system interface is provided
which is compatible with many microprocessor or system
busses, easing the integration of the 84C300A into many
system architectures. Its 32-bit data path width s provided
to provide the bandwidth necessary to maintain full duplex
wire speed communications simultaneously through all
four ports. Each port s provided with dual 128 byte FIFOs
to ease bus multiplexing and interfacing to different clock
domains.
NOTE:
Field length bytes, in parentheses.
FIRST BYTE
LAST BYTE
DESTINATION
ADDRESS
(6 BYTES)
SOURCE
ADDRESS
(6 BYTES)
BYTE COUNT
(2 BYTES)
DATA
(46 – 1500
BYTES)
A7
A15
A23
A31
A39
A47
B7
B15
B23
B31
B39
B47
T7
T15
D7
A0
A8
A16
A24
A32
A40
B0
B8
B16
B24
B32
B40
T0
T8
D0
. . . . . .
. . . . . .
. . . . . .
. . . . . .
. . . . . .
. . . . . .
. . . . . .
. . . . . .
. . . . . .
. . . . . .
. . . . . .
. . . . . .
. . . . . .
. . . . . .
. . . . . .
Typical Frame Buffer Format for
Byte-Organized Memory
PREAMBLE
(8)
DESTINATION
ADDRESS
(6)
SOURCE
ADDRESS
(6)
BYTE
COUNT
(2)
DATA
(46-1500)
FCS
(4)
ETHERNET FRAME
相關(guān)PDF資料
PDF描述
84C30A 84C30A 10 Mbps Controller (MAC) manual 12/96
84C300A 4-Port Fast Ethernet Controller(四端口快速以太網(wǎng)控制器)
84CNQ035 Schottky Rectifier
84CNQ040 Schottky Rectifier
84CNQ045 Schottky Rectifier
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
84C30A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:84C30A 10 Mbps Controller (MAC) manual 12/96
84C3A-A12-J06 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
84C3A-A12-J06L 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
84C3A-A12-J08L 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
84C3A-A12-J10L 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
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