參數(shù)資料
型號(hào)： 84C300A
英文描述： 84C300A 4-Port Fast Ethernet Controller manual 3/98
中文描述： 84C300A 4端口快速以太網(wǎng)控制器手冊(cè)3 / 98
文件頁(yè)數(shù)： 15/56頁(yè)
文件大小： 523K
代理商： 84C300A
84C300A 4-Port
Fast Ethernet Controller
4-15
MD400152/E
written to the port’s transmit FIFO by the system. Similarly,
a port can be prevented from appending an FCS value to
a packet by setting bit #4 HIGH in the Configuration
Register #1. As long as this bit is high, any packet
transmitted by he port will not nclude an FCS value unless
it is written as part of the transmit data written to the port's
transmit FIFO. Appending of a FCS value can be con-
trolled on a packet per packet basis by using the
TXNOCRC pin as long as the TXNOCRC Tx-Rx Configu-
ration register bit has not been set high. If the TXNOCRC
pin is held high (or) if the TXNOCRC bit is set anytime
during the duration of a packet write to the transmit FIFO,
that particular packet will not be appended with a CRC
value.
Transmit No CRC
H/W Pin 41
CRC Appendage
To the Packet
S/W Bit 4
of Config 1
0
1
0
1
0
0
1
1
Yes
No
No
No
Please note that both the H/W pin and the software bit
should be kept deasserted during the entire duration of the
packet write to the transmit FIFO in order to transmit a
packet with CRC.
3.2.2 Transmission Initiation in Full Duplex and
CSMA/CD Networks
Packet transmission begins with one of the following
conditions:
1. Data in the transmit FIFO meets or exceed a user-
defined threshold value or,
2. An EOF is asserted with the last data word written
into the transmit FIFO.
The transmit threshold value s controlled by programming
bits 7 through 4 of the Transmit Control/Product ID regis-
ter. The default value is 0 (zero), which enables the MAC
to begin packet transmission with as little as one double
word in the FIFO. The threshold, measured in double
words, is equal to the number programmed into Transmit
Control Register times 2. Thus, f the register contains the
value 3H, transmission is deferred until there are at least
6 double words of data in the FIFO.
Packet transmission initiation is also dependent upon
whether the 84C300A s n Full Duplex or CSMA/CD mode.
If he Chip s n CSMA/CD mode, ransmission may also be
prevented or delayed due to activity on the shared network
Preamble:
The preamble is a 64-bit field consisting
of 62 alternating “1”s and “0”s followed by a “11” End-
of-Preamble indicator.
Destination Address:
The Destination Address is a
6-byte field containing either a specific Station
Address, a Broadcast Address, or a Multicast
Address to which this frame is directed.
Source Address:
The Source Address is a 6-byte
field containing the specific Station Address from
which this frame originated.
Byte-Count Field:
The Byte-Count Field consists of
two bytes providing the number of valid data bytes in
the Data Field, 46 to 1500. This field is uninterpreted
at the Data Link Layer, and is passed through the
EDLC chip to be handled at the Client Layer.
Data Field:
The Data Field consists of 46 to 1500
bytes of information which are fully transparent in the
sense hat any arbitrary sequence of bytes may occur.
Frame Check Sequence:
The Frame Check
Sequence (FCS) field is a 32-bit cyclic redundancy
check (CRC) value computed as a function of the
Destination Address Field, Source Address Field,
Type Field and Data Field. The FCS is appended to
each transmitted frame, and used at reception to
determine if the received frame is valid.
3.2 PACKET TRANSMISSION PER PORT
The transmit data stream consists of the Preamble, four
information fields, and the FCS which is computed in real
time by the port and automatically appended to the frame
at the end of the data. The Preamble is also generated by
the port and transmitted immediately prior to the Destina-
tion Address. Destination Address, Source Address, Type
Field and Data Field are prepared in the buffer memory
prior to initiating transmission. The port encapsulates
these fields nto an Ethernet frame by nserting a preamble
prior o hese nformation ields and appending a CRC after
the information fields. A port can be programmed to
exclude nclusion of the preamble and/or the FCS from the
transmit data stream. In this case, it is assumed that the
preamble and FCS are provided as part of the data written
to the port.
3.2.1 Controlling Transmit Packet Encapsulation
As was mentioned n he previous paragraph, a port can be
programmed for exclusion of the FCS and/or the preamble
when ransmitting a packet. To program a port or ransmit-
ting a packet without creating a preamble, bit #2 of the
port’s Configuration Register #1 can be written high. Once
this bit is set, all packets transmitted by the port will not
include a preamble pattern unless it is part of the data
相關(guān)PDF資料
PDF描述
84C30A 84C30A 10 Mbps Controller (MAC) manual 12/96
84C300A 4-Port Fast Ethernet Controller(四端口快速以太網(wǎng)控制器)
84CNQ035 Schottky Rectifier
84CNQ040 Schottky Rectifier
84CNQ045 Schottky Rectifier
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
84C30A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:84C30A 10 Mbps Controller (MAC) manual 12/96
84C3A-A12-J06 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
84C3A-A12-J06L 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
84C3A-A12-J08L 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
84C3A-A12-J10L 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
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