參數(shù)資料
型號(hào)： 84C300A
英文描述： 84C300A 4-Port Fast Ethernet Controller manual 3/98
中文描述： 84C300A 4端口快速以太網(wǎng)控制器手冊(cè)3 / 98
文件頁(yè)數(shù)： 16/56頁(yè)
文件大?。?/td> 523K
代理商： 84C300A
84C300A 4-Port
Fast Ethernet Controller
4-16
MD400152/E
medium. If the network s not busy due to other data traffic,
transmission will begin after the appropriate defer time
(from end of previous traffic) has expired. Otherwise,
transmission is delayed until after current data transfers
are complete, and the defer time requirements have been
satisfied. Following the IEEE 802.3 specifications, the
minimum defer ime s split nto wo periods. The beginning
of the defer time occurs upon the transmitter sensing
carrier sense going LOW. Once this case occurs then if
carrier sense is reasserted during the 1st period of the
defer time, the transmitter will reset its defer time counter
and restart the total defer timeout period from 0. If carrier
sense s reasserted during the 2nd period of the total defer
time interval, the transmitter will ignore carrier sense and
start ransmission as soon as he defer ime s met. The 1st
period of the total defer time s programmable through use
of the transmit defer register. The second period of the
defer time nterval s either 3.2
μ
s or 0.32
μ
s depending on
whether the chip is in 10Mbit/sec or 100Mbit/sec mode.
The total default defer time for 10Mbit/sec serial mode is
9.6
μ
s as measured from TXEN going LOW to TXEN going
High assuming the transmit defer register is at 00 hex and
assuming that the TXEN going LOW to CSN going LOW
delay of the physical device is less than 5 TXC clock
periods. When the chip is in Full Duplex mode, transmis-
sion of data onto the network occurs independent of
whether carrier sense indicates a busy network condition
or not.
Because of the variability in delays given for TXEN going
LOW o CSN going LOW or different 100Mbit/sec physical
devices, the default defer time in 100 Mbit/sec MII mode
has been set assuming ull duplex conditions where carrier
sense is not monitored by the transmitter. In this case the
default is 0.96
μ
s from TXEN going LOW to TXEN going
HIGH. To adjust the defer time to some other value, the
programmable defer register can be set using he ormulas
given in the section describing the defer register. When
transmission begins, the chip activates the transmit en-
able (TXEN) line concurrently with the transmission of the
first bit, or first nibble in the MII case, of the Preamble and
keeps it active for the duration of the transmission.
3.2.3 Collision on Transmit
On the occurrence of a transmit collision condition that
does not represent the 16th transmission attempt for the
packet or does not occur after 64 byte times into the
transmission, the controller will automatically attempt to
retransmit the packet. First, the controller will halt the
transmission of data from the FIFO and begin transmitting
a Jam pattern consisting of 55555555 hex. The controller
will also reset the Transmit FIFO read address pointer
back to the beginning of the transmit packet within the
FIFO. At the end of transmitting the Jam pattern the
controller will then begin the Backoff wait period. Once the
backoff period is finished the controller will automatically
retransmit the packet. If a packet reaches 16 retransmis-
sion attempts without success due to collisions, or if a
collision occurs ater han 64 Byte imes after he beginning
of a transmission, this s considered to represent a serious
network error. Upon any one of these two error conditions
occurring, the selected port’s Transmit FIFO will be
cleared and the corresponding TXRET output will be
driven HIGH. If the TXRET signal was driven HIGH due to
16 transmission attempts, Bit ‘2’ of the transmit status
register gets set ndicating the occurrence of 16 collisions.
When either of the two above error conditions occurs,
retransmission of any packets that were in the transmit
FIFO requires first clearing the TXRET error condition and
then reloading the packet or packets n the Transmit FIFO.
Scheduling of retransmission is determined by a con-
trolled randomization process called Truncated Binary
Exponential Backoff. The chip waits a random interval
between 0 and 2
K
slot times (51.2
μ
s per slot time for 10
Mbit Ethernet or 5.12
μ
s per slot ime or 100 Mbit Ethernet)
before attempting retransmission, where “K” s the current
transmission attempt number (not to exceed 10).
3.2.4 Transmit Termination Conditions
A port will terminate transmission under the following
conditions.
Normal:
The frame has been transmitted success
fully without contention. Loading of the last data byte
into a port’s Transmit FIFO is signaled to the port by
activation of ts RxTxEOF signal concurrently with the
last double word of data loaded into the Transmit
FIFO. This ine acts as a thirty-third bit n the Transmit
FIFO. When the ast valid byte of the ast double word
has been transmitted, if the port is not in Transmit No
CRC mode, then the CRC is appended and transmit-
ted concluding frame transmission. The Transmis-
sion Successful bit of he Transmit Status Register will
be set by a normal termination.
Collision:
Transmission attempted by two or more
Ethernet nodes. The Jam sequence is transmitted,
the Collision status bit is set, transmit Collision
Counter is updated, the Backoff interval begun, and
the Transmit FIFO address is set to point to the
beginning of the packet for retransmission.
Underflow:
Transmit data is not ready when needed
for transmission. Once transmission has begun, a
port on average requires one transmit double word
every 3200 ns for 10 Mbit Ethernet or 320 ns for 100
Mbit Ethernet in order to avoid Transmit FIFO under
flow (starvation). If this condition occurs, the port ter-
minates the transmission, issues a TXRET signal,
and sets the Transmit-Underflow status bit.
相關(guān)PDF資料
PDF描述
84C30A 84C30A 10 Mbps Controller (MAC) manual 12/96
84C300A 4-Port Fast Ethernet Controller(四端口快速以太網(wǎng)控制器)
84CNQ035 Schottky Rectifier
84CNQ040 Schottky Rectifier
84CNQ045 Schottky Rectifier
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
84C30A 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:84C30A 10 Mbps Controller (MAC) manual 12/96
84C3A-A12-J06 制造商:BOURNS 制造商全稱(chēng):Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
84C3A-A12-J06L 制造商:BOURNS 制造商全稱(chēng):Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
84C3A-A12-J08L 制造商:BOURNS 制造商全稱(chēng):Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
84C3A-A12-J10L 制造商:BOURNS 制造商全稱(chēng):Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
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