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參數(shù)資料
| 型號： | 84C300A |
| 英文描述： | 84C300A 4-Port Fast Ethernet Controller manual 3/98 |
| 中文描述： | 84C300A 4端口快速以太網(wǎng)控制器手冊3 / 98 |
| 文件頁數(shù)： | 26/56頁 |
| 文件大小： | 523K |
| 代理商： | 84C300A |
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84C300A 4-Port
Fast Ethernet Controller
4-26
MD400152/E
3.6.4 Transmit Status Register
Within each port's transmit section are 2 transmit status
registers. These registers give the appearance of a single
register to an external CPU. With each transmission at-
tempt, whether successful or not, one of the status regis-
ters is written with the transmit status for that packet and
bit 7 of that register is set to a 0 until both registers are full.
When both registers are full, no new transmit status can be
written until one of the registers is read. To an external
CPU, both transmit status registers appear as a single
register. If the CPU reads a LOW value for bit 7 of the
transmit status register, this indicates that either one or
both of the nternal transmit registers contains new status.
A delay ime after he highgoing edge of he read operation
that reads new transmit status, one of the nternal transmit
status registers will be cleared and made available for new
transmit status. Following are the types of transmit status
given through status register:
A port can be programmed so hat f both ransmit registers
are full, no new transmissions will occur until at least one
of the register is cleared by reading it. To program this
feature, bit #1 of configuration register #2 needs to be
written to a 1 value.
Also a port can be programmed so that no new transmit
status is loaded if the transmission is successful.
7
6
5
4
3
2
1
0
Transmit Status Register Format
Bit
Value
Definition
R/W
Value After
Reset
0
‘1’
Indicates the occurrence of a
Transmit FIFO underflow.
R
0
1
‘1’
Indicates the occurrence of a
collision during a transmission
attempt.
R
0
2
‘1’
Indicates that 16 collisions
occurred while attempting to
transmit a packet.
R
0
3
‘1’
Indicates the successful
completion of a packet
tranmission.
R
0
4
‘1’
Indicates the occurrence of a
carrier sense error during a
transmission attempt.
R
0
5
‘1’
Indicates the occurrence of a
deferred transmission due to
carrier sense being detected HIGH.
R
0
6
‘1’
Indicates the occurrence of a late
collision. Late collision is the
occurrence of a transmit collision
64 byte times after TXEN went
HIGH.
R
0
7
‘1’
Indicates old/new status.
R
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 84C30A | 84C30A 10 Mbps Controller (MAC) manual 12/96 |
| 84C300A | 4-Port Fast Ethernet Controller(四端口快速以太網(wǎng)控制器) |
| 84CNQ035 | Schottky Rectifier |
| 84CNQ040 | Schottky Rectifier |
| 84CNQ045 | Schottky Rectifier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 84C30A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:84C30A 10 Mbps Controller (MAC) manual 12/96 |
| 84C3A-A12-J06 | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J06L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J08L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J10L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
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