參數(shù)資料
型號： 03H5716
元件分類： 通信及網(wǎng)絡(luò)
英文描述： SPECIALTY TELECOM CIRCUIT, PQFP100
封裝： 14 X 20 MM, 2.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, FP-100
文件頁數(shù)： 9/70頁
文件大小： 547K
代理商： 03H5716
Product Part Number: IBM22-ALDC1020S-01
ALDC1-20S-HA
I B M Microelectronics Division
Document Number: DCAL2HDSU-02
Data Compression
3.1.7 Error Status (ERRS)
The Error Status register provides error status
bits to the microprocessor. ERRS is reset to
X'0000' by a hardware or software reset.
This register is only accessable when CMND is
not equal to X'C100',X'C200',X'C400',or
X'C800'.
When MMODE equals B'0', use +ADDR(4:0) equals
X'0C' to read ERRS(7:0); and +ADDR(4:0) equals
X'0D' to read ERRS(15:8).
When MMODE equals B'1', use +ADDR(4:0) equals
X'0D' to read ERRS(7:0); and +ADDR(4:0) equals
X'0C' to read ERRS(15:8).
Figure
3-7. TCC
Figure
3-8. ERRS
BIT
NAME/NOTES
BIT
NAME/NOTES
31:16
Compressed Data Interface
Transfer Count High
4
Microprocessor Interface Parity
Error
This bit is set to B'1' when a
parity error is detected during a
microprocessor write to
+MDATA(15:00) and +MENABLEP is
tied high. It is reset to B'0'
when a data transfer operation
begins or when a reset occurs.
15:0
Compressed Data Interface
Transfer Count Low
3
Compressed Data Interface
Transfer Count (TCC) Overflow
Error
This bit is set to B'1' when a
carry out is detected on the
Compressed Data Interface
Transfer Count (TCC) register. It
is reset to B'0' when a data
transfer operation begins or
when a reset occurs.
2
Original Data Interface Transfer
Count (TCO) Overflow Error
This bit is set to B'1' when a
carry out is detected on the Ori-
ginal Data Interface Transfer
Count (TCO) register. It is reset
to B'0' when a data transfer
operation begins or when a reset
occurs.
Figure
3-8. ERRS
BIT
NAME/NOTES
15:7
Reserved
6
Original Data Interface Parity
Error
This bit is set to B'1' when a
parity error is detected during a
transfer into +ODATA(15:00) and
the original data interface Parity
(OCNF(15)) bit is set to B'1'.It
is reset to B'0' when a data
transfer operation begins or
when a reset occurs.
1
ALDC Decoder Control Code
Error
This bit is set to B'1' during
decompression when an invalid
control code is detected in the
compressed data stream. It is
reset to B'0' when a data
transfer operation begins or
when a reset occurs.
5
Compressed Data Interface
Parity Error
This bit is set to B'1' when a
parity error is detected during a
transfer into +CDATA(15:00) and
the compressed data interface
Parity (CCNF(15)) bit is set to
B'1'. It is reset to B'0' when a
data transfer operation begins or
when a reset occurs.
0
ALDC Decoder End Error
This bit is set to B'1' during
decompression when an End
control code is detected while
Compressed Data Interface
Transfer Count (TCC) is less than
Transfer Size (XFR) or when TCC
equals XFR and no End control
code is detected in the com-
pressed data stream. It is reset
to B'0' when a data transfer
operation begins or when a reset
occurs.
(C) IBM CORP. 1993, 1994. ALL RIGHTS RESERVED. USE IS FURTHER SUBJECT TO THE PROVISIONS ON THE BACK OF THE TITLE PAGE.
3-7
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