參數(shù)資料
型號(hào)： 03H5716
元件分類： 通信及網(wǎng)絡(luò)
英文描述： SPECIALTY TELECOM CIRCUIT, PQFP100
封裝： 14 X 20 MM, 2.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, FP-100
文件頁數(shù)： 13/70頁
文件大?。?/td> 547K
代理商： 03H5716
Product Part Number: IBM22-ALDC1020S-01
ALDC1-20S-HA
I B M Microelectronics Division
Document Number: DCAL2HDSU-02
Data Compression
3.1.10 Transfer Size (XFR)
The Transfer Size register provides the micro-
processor control of the number of bytes trans-
ferred during a data transfer operation.
Transfer Size (XFR) is a four byte register with
the two most significant bytes contained in
Transfer Size High (XFRH) and the two least
significant bytes contained in Transfer Size Low
(XFRL). XFRL and XFRH are reset to X'0000'
by a hardware or software reset.
When MMODE equals B'0', use +ADDR(4:0) equals
X'14' to read and write XFRH(7:0); +ADDR(4:0)
equals X'15' to read and write XFRH(15:8);
+ADDR(4:0) equals X'16' to read and write
XFRL(7:0); and +ADDR(4:0) equals X'17' to read
and write XFRL(15:8).
When MMODE equals B'1', use +ADDR(4:0) equals
X'15' to read and write XFRH(7:0); +ADDR(4:0)
equals X'14' to read and write XFRH(15:8);
+ADDR(4:0) equals X'17' to read and write
XFRL(7:0); and +ADDR(4:0) equals X'16' to read
and write XFRL(15:8).
The direction of the data transfer operation
specifies whether the Original Data Interface
Transfer Count (TCO) register or the Com-
pressed Data Interface Transfer Count (TCC)
register is used to determine when all data
bytes have been received for the data transfer
operation. During compression, TCO is used.
During decompression, TCC is used. When the
appropriate Transfer Count register (TCO or
TCC) equals XFR, all bytes in the current data
transfer operation have been received by
ALDC1-20S-HA.
Note: XFR is a thirty-two bit register. This
means that the maximum data block size which
can be specified is X'FFFF FFFF' (or
4,294,967,295) bytes. Therefore, the application
or system designer must ensure that data is
partitioned into data blocks smaller than 4
gigabytes, and that each data block is com-
pressed and decompressed separately.
3.1.11 Data Disable Count (DDC)
The Data Disable Count register provides the
microprocessor control of the number of bytes
skipped during a Start Decompression Output
Disabled (CMND equals X'6C00') operation.
Data Disable Count (DDC) is a four byte register
with the two most significant bytes contained in
Data Disabled Count High (DDCH) and the two
least significant bytes contained in Data Disa-
bled Count Low (DDCL). DDCL and DDCH are
reset to X'0000' by a hardware or software
reset.
When MMODE equals B'0', use +ADDR(4:0) equals
X'18' to read and write DDCH(7:0); +ADDR(4:0)
equals X'19' to read and write DDCH(15:8);
+ADDR(4:0) equals X'1A' to read and write
DDCL(7:0); and +ADDR(4:0) equals X'1B' to read
and write DDCL(15:8).
When MMODE equals B'1', use +ADDR(4:0) equals
X'19' to read and write DDCH(7:0); +ADDR(4:0)
equals X'18' to read and write DDCH(15:8);
+ADDR(4:0) equals X'1B' to read and write
DDCL(7:0); and +ADDR(4:0) equals X'1A' to read
and write DDCL(15:8).
Note: If the Data Disable Count (DDC) is set to
X'0000' during a Start Decompression Output
Disabled (CMND equals X'6C00') operation or
the DDC is greater than the Transfer Size (XFR)
during a Start Decompression Output Disabled
(CMND equals X'6C00') operation, then the ori-
ginal data interface output will be disabled for
the entire transfer.
Figure
3-11 (Page 3 of 3). Opcodes.
Note: Opcodes not explicitly
named in this table are reserved
for future use. They are invalid for
ALDC1-20S-HA and will produce no
operation.
OPCODE
NAME/NOTES
X'C800'
Select Compressed Data
Interface Peripheral Access
All peripheral access
addresses (+ADDR(4) equals
B'0') are enabled for reads
and writes to an compressed
data interface attached
peripheral.
Figure
3-12. XFR
BIT
NAME/NOTES
31:16
Transfer Size High (XFRH)
15:0
Transfer Size Low (XFRL)
(C) IBM CORP. 1993, 1994. ALL RIGHTS RESERVED. USE IS FURTHER SUBJECT TO THE PROVISIONS ON THE BACK OF THE TITLE PAGE.
3-10
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