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| 型號： | 03H5716 |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | 14 X 20 MM, 2.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, FP-100 |
| 文件頁數(shù)： | 15/70頁 |
| 文件大小： | 547K |
| 代理商： | 03H5716 |
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Product Part Number: IBM22-ALDC1020S-01
ALDC1-20S-HA
I B M Microelectronics Division
Document Number: DCAL2HDSU-02
Data Compression
When MMODE equals B'1', use +ADDR(4:0) equals
X'1F' to read IMSK(7:0); and +ADDR(4:0) equals
X'1E' to read IMSK(15:8).
Note: The microprocessor disables interrupts
by setting bits in IMSK. When interrupts are
disabled, it is the microprocessor responsibility
to ensure that the correct STAT bits are polled.
3.2 Interrupts
There are two hardware interrupt signals for
ALDC1-20S-HA. One is -IREQOD, which is a neg-
ative active, open-drain output. The other is
+IREQPP; a positive active, push-pull output.
When active, they indicate that a data transfer
operation has completed successfully, has been
held, or has failed.
The microprocessor can determine if the data
transfer operation failed by reading and testing
the Any Error (STAT(1)) bit. If the Any Error bit
is set to a B'1', then an error occurred in the
previously attempted data transfer operation.
The cause of the error can be determined by
reading the Error Status (ERRS) register. Error
recovery procedures may then be invoked as
appropriate.
If the Any Error bit is B'0', then no error
occurred in the previous data transfer opera-
tion.
Likewise, the microprocessor can determine if
the data transfer operation was held by reading
and testing the Hold (STAT(6)) bit. If the Hold
bit is set to a B'1', then the data transfer oper-
ation is held and waiting to be resumed.
If both the Any Error bit and the Hold bit are
B'0' and the Done (STAT(0)) bit is a B'1', then
the data transfer operation completed success-
fully.
The hardware interrupt signals automatically
return to their inactive state when either a
hardware reset or a software reset occurs,
when a data transfer operation is resumed, or
when a new data transfer operation begins.
Note: -IREQOD is an open-drain output and
requires a pull-up resistor. See section
Chapter 6 on page 6-1 for pull-up resistor
selection considerations.
3.3 Resets
There is one hardware reset signal for
ALDC1-20S-HA (-RESET). When asserted, all
registers (except the EC Level register) are
reset, current operations are cancelled, and the
history buffer is cleared.
There is also one software reset for
ALDC1-20S-HA (CMND equals X'A000'). The
software reset does not affect the Original Data
Interface Configuration (OCNF), Compressed
Data Interface Configuration (CCNF), EC Level
(ECL), Original Data Interface Polarity (OPOL),
Compressed Data Interface Polarity (CPOL), or
Command (CMND) registers. All other regis-
ters are reset, current operations are cancelled,
and the history buffer is cleared.
Figure 3-16 summarizes the hardware and soft-
ware resets for ALDC1-20S-HA. Because some
register's contents are modified during initial-
ization for data transfer operations, this infor-
mation is also included in the figure.
Figure
3-15. IMSK
BIT
NAME/NOTES
15:8
Reserved
7
Done Interrupt Mask
When set to a B'1', the corre-
sponding Done Interrupt (INTS(7))
bit is disabled. When reset to a
B'0', the Done Interrupt is re-
enabled.
6
Hold Interrupt Mask
When set to a B'1', the corre-
sponding Hold Interrupt (INTS(6))
bit is disabled. When reset to a
B'0', the Hold Interrupt is re-
enabled.
5:1
Reserved
0
Error Interrupt Mask
When set to a B'1', the corre-
sponding Error Interrupt (INTS(0))
bit is disabled. When reset to a
B'0', the Error Interrupt is re-
enabled.
(C) IBM CORP. 1993, 1994. ALL RIGHTS RESERVED. USE IS FURTHER SUBJECT TO THE PROVISIONS ON THE BACK OF THE TITLE PAGE.
3-12
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