參數(shù)資料
型號： 03H5716
元件分類： 通信及網(wǎng)絡(luò)
英文描述： SPECIALTY TELECOM CIRCUIT, PQFP100
封裝： 14 X 20 MM, 2.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, FP-100
文件頁數(shù)： 53/70頁
文件大小： 547K
代理商： 03H5716
Product Part Number: IBM22-ALDC1020S-01
ALDC1-20S-HA
I B M Microelectronics Division
Document Number: DCAL2HDSU-02
Data Compression
Figure
5-2 (Page 5 of 6). Preliminary Pin Description. For the ALDC1-20S-HA. See Figure 5-1 on
page 5-1 to identify pin locations.
PIN
NAME
I/O
DESCRIPTION
S18
+CDATA(13)
bid
The compressed data interface data bit 13 pin. May be
tied high, tied low, or not connected when not enabled.
+CDATA(13) is enabled by setting CCNF(10) to B'1'.
S19
+CDATA(12)
bid
The compressed data interface data bit 12 pin. May be
tied high, tied low, or not connected when not enabled.
+CDATA(12) is enabled by setting CCNF(10) to B'1'.
S20
Vdd
A + 5 Volt power supply pin.
S21
GND
A ground pin.
S22
+CDATA(11)
bid
The compressed data interface data bit 11 pin. May be
tied high, tied low, or not connected when not enabled.
+CDATA(11) is enabled by setting CCNF(10) to B'1'.
S23
+CDATA(10)
bid
The compressed data interface data bit 10 pin. May be
tied high, tied low, or not connected when not enabled.
+CDATA(10) is enabled by setting CCNF(10) to B'1'.
S24
+CDATA(09)
bid
The compressed data interface data bit 9 pin. May be
tied high, tied low, or not connected when not enabled.
+CDATA(09) is enabled by setting CCNF(10) to B'1'.
S25
+CDATA(08)
bid
The compressed data interface data bit 8 pin. May be
tied high, tied low, or not connected when not enabled.
+CDATA(08) is enabled by setting CCNF(10) to B'1'.
S26
+CPARITY(0)
bid
The compressed data interface parity bit 0 pin. When
enabled, this pin checks parity on input and generates
parity on output for the associated +CDATA(00) through
+CDATA(07) pins. May be tied high, tied low, or not con-
nected when not enabled.
+CPARITY(0) is enabled by setting CCNF(15) to B'1'.
S27
+CPARITY(1)
bid
The compressed data interface parity bit 1 pin. When
enabled, this pin checks parity on input and generates
parity on output for the associated +CDATA(08) through
+CDATA(15) pins. May be tied high, tied low, or not con-
nected when not enabled.
+CPARITY(1) is enabled by setting CCNF(15) and
CCNF(10) to B'1'.
S28
Vdd
A + 5 Volt power supply pin.
S29
GND
A ground pin.
S30
-IREQOD
out
The microprocessor interface open-drain interrupt
request pin.
Note: -IREQOD is an open-drain output and requires a
pull-up resistor if used. See Chapter 6 on page 6-1 for
pull-up resistor selection considerations.
E01
+IREQPP
out
The microprocessor interface push-pull interrupt
request pin.
(C) IBM CORP. 1993, 1994. ALL RIGHTS RESERVED. USE IS FURTHER SUBJECT TO THE PROVISIONS ON THE BACK OF THE TITLE PAGE.
5-5
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