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參數(shù)資料
| 型號： | 03H5716 |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | 14 X 20 MM, 2.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, FP-100 |
| 文件頁數(shù)： | 4/70頁 |
| 文件大?。?/td> | 547K |
| 代理商： | 03H5716 |
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Product Part Number: IBM22-ALDC1020S-01
ALDC1-20S-HA
I B M Microelectronics Division
Document Number: DCAL2HDSU-02
Data Compression
Figure
3-1 (Page 2 of 2). Register Summary
+ADDR(4:1)
MNEMONIC
REGISTER NAME
PAGE
R/ W
X'F'
IMSK
Interrupt Mask
3-11
R/ W
Notes:
1. When CMND is not equal to X'C100',X'C200',X'C400',or X'C800'.
2. When CMND equals X'C100'.
3. When CMND equals X'C200'.
3.1.1 Status (STAT)
The Status register provides status bits to the
microprocessor. STAT is reset to X'0000' by a
hardware or software reset.
This register is only accessable when CMND is
not equal to X'C100',X'C200',X'C400',or
X'C800'.
If MMODE equalsB'0' use +ADDR(4:0) equals X'00'
to read STAT(7:0); and +ADDR(4:0) equals X'01'
to read STAT(15:8).
If MMODE equalsB'1' use +ADDR(4:0) equals X'01'
to read STAT(7:0); and +ADDR(4:0) equals X'00'
to read STAT(15:8).
Figure
3-2 (Page 1 of 2). STAT
BIT
NAME/NOTES
5
Output Disabled
This bit is set to B'1' when ori-
ginal data interface output is dis-
abled. It is reset to B'0' when
original data interface output is
re-enabled or when a reset
occurs.
Note: The Start Decompression
Output Disabled (CMND equals
X'6C00') opcode and the Data
Disabled Count (DDC) register
are used to control original data
interface output disabling.
4
Bypass
This bit is set to B'1' when com-
pression and decompression are
disabled. It is reset to B'0'
when compression and decom-
pression are re-enabled or when
a reset occurs.
Note: The Start Compression
Bypass (CMND equals X'5000')
and Start Decompression Bypass
(CMND equals X'6000') opcodes
are used to control compression
and decompression disabling.
Figure
3-2 (Page 1 of 2). STAT
BIT
NAME/NOTES
15:8
Reserved
7
Busy
This bit is set to B'1' when a
data transfer operation is initi-
ated by the microprocessor. It is
reset to B'0' when the data
transfer operation completes
successfully, when an unmasked
error occurs, when a reset
occurs, or when a hold opcode is
issued by the microprocessor.
Important!
See ALDC1-20S-HA Design
Note 1 on page ii.
3
Expansion
This bit is set to B'1' when the
Compressed Data Interface
Transfer Count (TCC) register is
larger than the Transfer Size
(XFR) register at the end of a
compression operation. It is
reset to B'0' when another data
transfer operation begins or
when a reset occurs.
See section 3.4 on page 3-13 for
a discussion of data expansion.
6
Hold
This bit is set to B'1' when a
data transfer operation is cur-
rently held. It is reset to B'0'
when a held data transfer opera-
tion is resumed or when a reset
occurs.
(C) IBM CORP. 1993, 1994. ALL RIGHTS RESERVED. USE IS FURTHER SUBJECT TO THE PROVISIONS ON THE BACK OF THE TITLE PAGE.
3-2
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