參數(shù)資料
型號(hào)： 03H5716
元件分類： 通信及網(wǎng)絡(luò)
英文描述： SPECIALTY TELECOM CIRCUIT, PQFP100
封裝： 14 X 20 MM, 2.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, FP-100
文件頁數(shù)： 69/70頁
文件大?。?/td> 547K
代理商： 03H5716
Product Part Number: IBM22-ALDC1020S-01
ALDC1-20S-HA
I B M Microelectronics Division
Document Number: DCAL2HDSU-02
Data Compression
2.1.4 ALDC Encoder
The ALDC encoder accepts data bytes from the
original data interface and provides com-
pressed data bytes to the compressed data
interface. The ALDC implementation of the
adaptive Lempel-Ziv lossless compression
algorithm accomplishes this function.
The ALDC encoder contains a 512-byte content
addressable memory (CAM). The CAM is the
history buffer during compression operations.
The ALDC encoder concatenates an end
marker control code to the end of the com-
pressed data. It also pads any remaining bits
with zeros to align evenly on a byte boundary.
2.1.5 ALDC Decoder
The ALDC decoder accepts compressed data
bytes from the compressed data interface and
provides the reconstructed data bytes to the
original data interface. The ALDC implementa-
tion of the adaptive Lempel-Ziv lossless com-
pression algorithm accomplishes this function.
The ALDC decoder contains a 512-byte random
access memory (RAM). The RAM is the history
buffer during decompression operations.
The ALDC decoder expects to find an end
marker control code in the final data received
from the compressed data interface. If it does
not detect the end marker control code, then it
asserts an ALDC decoder end error. If it
detects the end marker control code, then it
strips the end marker control code from the
decompressed data stream.
2.2 Data Transfer Operations
The data transfer operations describe how data
may be transferred between the original data
interface and the compressed data interface.
The microprocessor interface controls the
internal sequencing of ALDC1-20S-HA to
accomplish the data transfer operations. The
data transfer operations are started when the
appropriate data transfer command is decoded
in the command register.
Data transfer operations typically involve blocks
of data bytes. These blocks may either have
fixed or variable length depending on the
desired application. The transfer size in bytes
is loaded into the appropriate microprocessor
interface register. The transfer proceeds until
the specified number of bytes are processed, a
hardware or software reset occurs, an error
occurs, or a hold opcode occurs.
After a data transfer operation has ended
(either successfully or unsuccessfully), the
microprocessor prepares ALDC1-20S-HA for the
next data transfer operation.
Note: Interrupts may be disabled by setting the
ALDC1-20S-HA Interrupt Mask register to
X'FFFF'. If interrupts are disabled, then the
microprocessor must poll the correct status bits
to determine the progress and outcome of a
data transfer operation.
2.2.1 General Data Transfer
Sequencing
This is the general control sequence which
occurs during data transfer operations:
1. The history buffer is cleared, the transfer
count registers are reset to X'000000', the
error status register is reset to X'0000',
and the status register is set to X'0080' (ie.
Busy).
2. The original data interface and compressed
data interface are enabled to send and
receive data as appropriate. Also, the
encoder or decoder bypass paths are set
up as appropriate.
3. Data is received and processed until the
end of data is reached. During processing,
the output data is sent as it becomes avail-
able.
4. When the end of data is reached at the
sending interface, the interrupt outputs are
asserted and the Done (STAT(0)) bit is set
to B'1'.
Exception Conditions: The following exception
conditions may prevent the general data
transfer sequence from completing:
If an error occurs during the data transfer
operation, then the interrupt output is
immediately asserted; the Any Error
(STAT(1)) bit is set to B'1'; the proper bit in
the error status (ERRS) register is also set
to B'1'; and the transfer is ended.
Depending on the type of error, the micro-
processor may attempt to retry the current
(C) IBM CORP. 1993, 1994. ALL RIGHTS RESERVED. USE IS FURTHER SUBJECT TO THE PROVISIONS ON THE BACK OF THE TITLE PAGE.
2-2
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