參數(shù)資料
型號(hào)： 03H5716
元件分類： 通信及網(wǎng)絡(luò)
英文描述： SPECIALTY TELECOM CIRCUIT, PQFP100
封裝： 14 X 20 MM, 2.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, FP-100
文件頁數(shù)： 14/70頁
文件大?。?/td> 547K
代理商： 03H5716
Product Part Number: IBM22-ALDC1020S-01
ALDC1-20S-HA
I B M Microelectronics Division
Document Number: DCAL2HDSU-02
Data Compression
3.1.12 Error Mask (EMSK)
The Error Mask register provides error
reporting configuration capability to the micro-
processor. EMSK is reset to X'0000' by a hard-
ware or software reset.
When MMODE equals B'0', use +ADDR(4:0) equals
X'1C' to read EMSK(7:0); and +ADDR(4:0) equals
X'1D' to read EMSK(15:8).
When MMODE equals B'1', use +ADDR(4:0) equals
X'1D' to read EMSK(7:0); and +ADDR(4:0) equals
X'1C' to read EMSK(15:8).
3.1.13 Interrupt Mask (IMSK)
The Interrupt Mask register provides interrupt
reporting configuration capability to the micro-
processor. IMSK is reset to X'0000' by a hard-
ware or software reset.
When MMODE equals B'0', use +ADDR(4:0) equals
X'1E' to read IMSK(7:0); and +ADDR(4:0) equals
X'1F' to read IMSK(15:8).
Figure
3-13. DDC
Figure
3-14. EMSK
BIT
NAME/NOTES
BIT
NAME/NOTES
31:16
Data Disabled Count High
(DDCH)
3
Compressed Data Interface
Transfer Count (TCC) Overflow
Error Mask
When set to a B'1', the corre-
sponding Compressed Data
Interface Transfer Count (TCC)
Overflow Error (ERRS(3)) bit is
disabled. When reset to a B'0',
the Compressed Data Interface
Transfer Count Overflow Error bit
is re-enabled.
15:0
Data Disabled Count Low (DDCL)
2
Original Data Interface Transfer
Count (TCO) Overflow Error
Mask
When set to a B'1', the corre-
sponding Original Data Interface
Transfer Count (TCO) Overflow
Error (ERRS(2)) bit is disabled.
When reset to a B'0', the Ori-
ginal Data Interface Transfer
Count Overflow Error bit is re-
enabled.
Figure
3-14. EMSK
BIT
NAME/NOTES
15:7
Reserved
1
ALDC Decoder Control Code
Error Mask
When set to a B'1', the corre-
sponding ALDC Decoder Control
Error (ERRS(1)) bit is disabled.
When reset to a B'0', the ALDC
Decoder Control Code Error bit is
re-enabled.
6
Original Data Interface Parity
Error Mask
When set to a B'1', the corre-
sponding Original Data Interface
Parity Error (ERRS(6)) bit is disa-
bled. When reset to a B'0', the
Original Data Interface Parity
Error bit is re-enabled.
0
ALDC Decoder End Error Mask
When set to a B'1', the corre-
sponding ALDC Decoder End
Error (ERRS(0)) bit is disabled.
When reset to a B'0', the ALDC
Decoder End Error bit is re-
enabled.
5
Compressed Data Interface
Parity Error Mask
When set to a B'1', the corre-
sponding Compressed Data
Interface Parity Error (ERRS(5))
bit is disabled. When reset to a
B'0', the Compressed Data
Interface Parity Error bit is re-
enabled.
4
Microprocessor Interface Parity
Error Mask
When set to a B'1', the corre-
sponding Microprocessor Inter-
face Parity Error (ERRS(4)) bit is
disabled. When reset to a B'0',
the Microprocessor Interface
Parity Error bit is re-enabled.
(C) IBM CORP. 1993, 1994. ALL RIGHTS RESERVED. USE IS FURTHER SUBJECT TO THE PROVISIONS ON THE BACK OF THE TITLE PAGE.
3-11
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