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| 型號： | 03H5716 |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | 14 X 20 MM, 2.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, FP-100 |
| 文件頁數(shù)： | 10/70頁 |
| 文件大?。?/td> | 547K |
| 代理商： | 03H5716 |
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Product Part Number: IBM22-ALDC1020S-01
ALDC1-20S-HA
I B M Microelectronics Division
Document Number: DCAL2HDSU-02
Data Compression
3.1.8 Interrupt Status (INTS)
The Interrupt Status register provides interrupt
status bits to the microprocessor. INTS is reset
to X'0000' by a hardware or software reset.
This register is only accessable when CMND is
not equal to X'C100',X'C200',X'C400',or
X'C800'.
When MMODE equals B'0', use +ADDR(4:0) equals
X'0E' to read INTS(7:0); and +ADDR(4:0) equals
X'0F' to read INTS(15:8).
When MMODE equals B'1', use +ADDR(4:0) equals
X'0F' to read INTS(7:0); and +ADDR(4:0) equals
X'0E' to read INTS(15:8).
See section 3.2 on page 3-12 for more informa-
tion on interrupts.
3.1.9 Command (CMND)
The Command register is used to program
operation of ALDC1-20S-HA. CMND is reset to
X'0000' by a hardware reset. CMND is not
changed by a software reset.
When MMODE equals B'0', use +ADDR(4:0) equals
X'10' to read and write CMND(7:0); and
+ADDR(4:0) equals X'11' to read and write
CMND(15:8).
When MMODE equals B'1', use +ADDR(4:0) equals
X'11' to read and write CMND(7:0); and
+ADDR(4:0) equals X'10' to read and write
CMND(15:8).
The CMND Register layout shown in
Figure 3-10 is defined in the opcode description
given in Figure 3-11.
Figure
3-9. INTS
BIT
NAME/NOTES
0
Error Interrupt
This bit is set to B'1' when an
error occurs. It is reset to B'0'
when a data transfer operation
begins or when a reset occurs.
Note: The Error Status (ERRS)
register is used to determine the
cause of the error.
Figure
3-9. INTS
BIT
NAME/NOTES
15:8
Reserved
7
Done Interrupt
This bit is set to B'1' when data
transfer has completed on the
compressed data interface
during compression and when
data transfer has completed on
the original data interface during
decompression. It is reset to
B'0' when a data transfer opera-
tion begins or when a reset
occurs.
Figure
3-10. CMND
BIT
NAME/NOTES
15:0
Opcode
See Figure 3-11 for proposed
opcode descriptions.
6
Hold Interrupt
This bit is set to B'1' when the
current transfer step after the
microprocessor issues a Hold
(CMND equals X'4200') opcode
is completed. It is reset to B'0'
when the microprocessor issues
a Resume (CMND equals
X'4400') opcode, when a data
transfer operation begins, or
when a reset occurs.
Figure
3-11 (Page 1 of 3). Opcodes.
Note: Opcodes not explicitly
named in this table are reserved
for future use. They are invalid for
ALDC1-20S-HA and will produce no
operation.
5:1
Reserved
OPCODE
NAME/NOTES
X'0000'
NOP
No operation is performed.
(C) IBM CORP. 1993, 1994. ALL RIGHTS RESERVED. USE IS FURTHER SUBJECT TO THE PROVISIONS ON THE BACK OF THE TITLE PAGE.
3-8
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