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535
CHAPTER 25 STAND-BY FUNCTION
Table 25-7. Operating States in IDLE Mode
IDLE Mode Setting
When there is a subsystem clock
When there is not a subsystem clock
Item
Clock generation circuit
The oscillation circuits in both the main system clock and subsystem clock continue
operating. The clock supply to both the CPU and peripherals is stopped.
CPU
Operation disabled
Port (output latch)
Saves the state before the IDLE mode was set
16-bit timer/counter
Operational when the watch timer output
is selected as the count clock (Select f
XT
as the count clock of the watch timer.)
Operation disabled
8-bit timer/counters 1, 2
Operational only when TI1 and TI2 are selected as the count clocks
8-bit timer/counters 5, 6
Operational only when TI5 and TI6 are selected as the count clocks
8-bit timer/counters 7, 8
Operational only when TI7 and TI8 are selected as the count clocks
Watch timer
Operational only when f
XT
is selected as
the count clock
Operation disabled
Watchdog timer
Operation disabled
A/D converter
Operation disabled
D/A converter
Operation enabled
Real-time output port
Operational when an external trigger is used or TI1 and TI2 are selected as the count
clocks of the 8-bit timer/counters 1 and 2
Serial interface
I
2
C bus mode
Operational only when an external input clock is selected as the serial clock
I
2
C bus mode
Operation disabled
External interrupt
INTP0 - INTP6
Operation enabled
Key return interrupt
P80 - P87
Operation enabled
Bus lines during
external expansionA0 - A19
AD0 - AD7
High impedance
Holds the state before the IDLE mode is set
ASTB
Low level
WR, RD
High level
WAIT
High impedance
Caution In the IDLE mode, only external interrupts (INTP0 to INTP6), watch timer interrupt (INTWT), and
key return interrupts (P80 to P87) can release the IDLE mode and be acknowledged as interrupt
requests. All other interrupt requests are pended, and acknowledged after the IDLE mode has
been released through NMI input, INTP0 to INTP6 input, INTWT, or key return interrupt.