![](http://datasheet.mmic.net.cn/380000/-PD784214Y_datasheet_16744924/-PD784214Y_24.png)
24
11-11
11-12
Start Timing of 8-Bit Timer ..................................................................................................................... 249
Timing After the Compare Register Changes During Timer Counting ................................................... 250
12-1
12-2
12-3
Block Diagram of Watch Timer .............................................................................................................. 252
Format of Watch Timer Mode Control Register (WTM) ......................................................................... 254
Operation Timing of Watch Timer/Interval Timer.................................................................................... 256
13-1
13-2
Watchdog Timer Block Diagram ............................................................................................................ 257
Watchdog Timer Mode Register (WDM) Format.................................................................................... 259
14-1
14-2
14-3
14-4
14-5
14-6
14-7
14-8
14-9
14-10
14-11
A/D Converter Block Diagram................................................................................................................ 264
A/D Converter Mode Register Format ................................................................................................... 267
A/D Converter Input Selection Register (ADIS) Format......................................................................... 268
Basic Operations of A/D Converter ........................................................................................................ 270
Relationship between Analog Input Voltage and A/D Conversion Result .............................................. 271
A/D Conversion Operation by Hardware Start (When Falling Edge is Specified).................................. 272
A/D Conversion Operation by Software Start ........................................................................................ 273
Method to Reduce Current Dissipation in Standby Mode ...................................................................... 274
Handling of Analog Input Pin ................................................................................................................. 275
A/D Conversion End Interrupt Generation Timing ................................................................................. 276
Handling of AVDD Pin ............................................................................................................................ 276
15-1
15-2
15-3
D/A Converter Block Diagram ................................................................................................................ 280
D/A Converter Mode Registers 0, 1 (DAM0, DAM1) Formats ............................................................... 281
Buffer Amp Insertion Example ............................................................................................................... 283
16-1
Serial Interface Example........................................................................................................................ 286
17-1
17-2
17-3
17-4
17-5
17-6
17-7
17-8
17-9
17-10
17-11
17-12
17-13
17-14
Switching Asynchronous Serial Interface Mode and 3-Wire Serial I/O Mode ........................................ 288
Block Diagram in Asynchronous Serial Interface Mode ......................................................................... 290
Asynchronous Serial Interface Mode Registers 1, 2 (ASIM1, ASIM2) Format ...................................... 293
Asynchronous Serial Interface Status Registers 1, 2 (ASIS1, ASIS2) Format ...................................... 294
Baud Rate Generator Control Registers 1, 2 (BRGC1, BRGC2) Format .............................................. 296
Baud Rate Capacity Error Considering Sampling Errors (When k = 0) ................................................. 303
Asynchronous Serial Interface Transmit/Receive Data Format ............................................................. 304
Asynchronous Serial Interface Transmit completion Interrupt Timing.................................................... 306
Asynchronous Serial Interface Receive Completion Interrupt Timing.................................................... 307
Receive Error Timing ............................................................................................................................. 308
Comparison of Infrared Data Transfer Mode and UART Mode Data Formats ....................................... 309
Block Diagram for the 3-Wire Serial I/O mode....................................................................................... 314
Serial Operation Mode Registers 1, 2 (CSIM1, CSIM2) Format ............................................................ 315
Serial Operation Mode Registers 1, 2 (CSIM1 CSIM2) Format ............................................................. 316
LIST OF FIGURES (4/8)
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