![](http://datasheet.mmic.net.cn/380000/-PD784214Y_datasheet_16744924/-PD784214Y_412.png)
412
CHAPTER 23 INTERRUPT FUNCTIONS
23.3.5 Watchdog timer mode register (WDM)
The WDT4 bit of the WDM specifies the priority of NMI pin input non-maskable interrupts and watchdog timer overflow
non-maskable interrupts.
The WDM can be written to only by a dedicated instruction. This dedicated instruction, MOV WDM, #byte, has a special
code configuration (4 bytes), and a write is not performed unless the 3rd and 4th bytes of the operation code are mutual
1’s complements.
If the 3rd and 4th bytes of the operation code are not mutual 1’s complements, a write is not performed and an operand
error interrupt is generated. In this case, the return address saved in the stack area is the address of the instruction that
was the source of the error, and thus the address that was the source of the error can be identified from the return address
saved in the stack area.
If recovery from an operand error is simply performed by means of an RETB instruction, an endless loop will result.
As an operand error interrupt is only generated in the event of an inadvertent program loop (with the NEC assembler,
RA78K4, only the correct dedicated instruction is generated when MOV WDM, #byte is written), system initialization should
be performed by the program.
Other write instructions (MOV WDM, A; AND WDM, #byte; and SET1 WDM.7) are ignored and do not perform any
operation. That is, a write is not performed to the WDM, and an interrupt such as an operand error interrupt is not generated.
The WDM can be read at any time by a data transfer instruction.
RESET input clears the WDM register to 00H.
Figure 23-5. Format of Watchdog Timer Mode Register (WDM)
Caution The watchdog timer mode register (WDM) can be written only by using a dedicated instruction (MOV
WDM, #byte).
WDM
RUN
7
6
5
4
3
2
1
0
0
WDT4
0
WDT2
WDT1
0
0
RUN
Address : 0FFC2H
Symbol
R/W
After Reset : 00H
Specifies operation of watchdog timer (refer to
Figure 13-2
).
WDT4
0
1
Priority of Watchdog Timer Interrupt Request
Watchdog timer interrupt request < NMI pin input interrupt request
Watchdog timer interrupt request > NMI pin input interrupt request
WDT2
WDT1
Specifies count clock of watchdog timer
(refer to
Figure 13-2
).