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25
17-15
17-16
Serial Operation Mode Registers 1, 2 (CSIM1, CSIM2) Format ............................................................ 317
3-Wire Serial I/O Mode Timing............................................................................................................... 318
18-1
18-2
18-3
18-4
18-5
Block Diagram of the Clock-Synchronized Serial Interface (in the 3-wire Serial I/O Mode) .................. 320
Serial Operating Mode Register 0 (CSIM0) Format............................................................................... 321
Serial Operating Mode Register 0 (CSIM0) Format............................................................................... 322
Serial Operating Mode Register 0 (CSIM0) Format............................................................................... 323
3-Wire Serial I/O Mode Timing............................................................................................................... 324
19-1
19-2
19-3
19-4
19-5
19-6
19-7
19-8
19-9
19-10
19-11
19-12
19-13
19-14
19-15
19-16
19-17
19-18
19-19
19-20
19-21
Serial Bus Configuration Example in I
2
C Bus Mode .............................................................................. 326
Block Diagram of Clock-synchronized Serial Interface (I
2
C Bus Mode)................................................. 327
I
2
C Bus Control Register (IICC0) Format ............................................................................................... 330
I
2
C Bus Status Register (IICS0) Format................................................................................................. 335
Format of the Prescaler Mode Register (SPRM0) for Serial Clock........................................................ 339
Pin Configuration ................................................................................................................................... 341
Serial Data Transfer Timing of I
2
C Bus .................................................................................................. 342
Start Condition ....................................................................................................................................... 342
Address.................................................................................................................................................. 343
Transfer Direction Specification ............................................................................................................. 344
Acknowledge Signal .............................................................................................................................. 345
Stop Condition ....................................................................................................................................... 346
Wait Signal ............................................................................................................................................. 347
Example of Arbitration Timing ................................................................................................................ 371
Timing of Communication Reservation .................................................................................................. 374
Communication Reservation Acceptance Timing .................................................................................. 374
Communication Reservation Procedure ................................................................................................ 375
Master Operating Procedure ................................................................................................................. 377
Slave Operating Procedure ................................................................................................................... 378
Master
Slave Communication Example (when master and slave select 9 clock waits) .................... 380
Slave
Master Communication Example (when master and slave select 9 clock waits) .................... 383
20-1
20-2
20-3
20-4
Remote Control Output Application Example ........................................................................................ 387
Clock Output Function Block Diagram ................................................................................................... 388
Clock Output Control Register (CKS) Format ........................................................................................ 389
Port 2 Mode Register (PM2) Format...................................................................................................... 390
21-1
21-2
21-3
Buzzer Output Function Block Diagram................................................................................................. 391
Clock Output Control Register (CKS) Format ........................................................................................ 392
Port 2 Mode Register (PM2) Format...................................................................................................... 393
22-1
Format of External Interrupt Rising Edge Enable Register (EGP0) and
External Interrupt Falling Edge Enable Register (EGN0) ...................................................................... 395
Edge Detection of P00 to P06 Pins ....................................................................................................... 396
22-2
LIST OF FIGURES (5/8)
Figure No.
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