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29
LIST OF TABLES (1/3)
Table No.
Title
Page
2-1
I/O Circuit Type for Each Pin and Handling Unused Pins ......................................................................
58
3-1
3-2
3-3
3-4
3-5
3-6
Vector Table Address .............................................................................................................................
Internal RAM Space List ........................................................................................................................
Settings of the Internal Memory Size Switching Register (IMS) ............................................................
Register Bank Selection ........................................................................................................................
Correspondence Between Function Names and Absolute Names ........................................................
Special Function Register (SFR) List.....................................................................................................
70
73
77
81
93
95
4-1
Clock Generator Configuration .............................................................................................................. 101
5-1
5-2
5-3
Port Functions........................................................................................................................................ 118
Port Configuration .................................................................................................................................. 119
Port Mode Register and Output Latch Settings when Using Alternate Functions.................................. 137
6-1
6-2
6-3
Real-time Output Port Configuration...................................................................................................... 145
Operations for Manipulating Real-time Output Buffer Registers............................................................ 147
Operating Modes and Output Triggers of Real-time Output Port........................................................... 149
7-1
Timer/Counter Operation ....................................................................................................................... 153
8-1
8-2
8-3
Configuration of 16-bit Timer/Counter (TM0) ......................................................................................... 158
Valid Edge of TI00 Pin and Valid Edge of Capture Trigger of Capture/Compare Register .................... 160
Valid Edge of TI01 Pin and Valid Edge of Capture Trigger of Capture/Compare Register .................... 160
9-1
8-Bit Timer/Counter 1, 2 Configuration .................................................................................................. 192
10-1
8-Bit Timer/Counter 5, 6 Configuration .................................................................................................. 212
11-1
8-Bit Timer/Counter 7, 8 Configuration .................................................................................................. 232
12-1
12-2
12-3
Interval Time of Interval Timer ............................................................................................................... 251
Configuration of Watch Timer ................................................................................................................ 252
Interval Time of Interval Timer ............................................................................................................... 255
14-1
A/D Converter Configuration.................................................................................................................. 263
15-1
D/A Converter Structure......................................................................................................................... 279
17-1
17-2
17-3
17-4
Designation Differences between UART1/IOE1 and UART2/IOE2 ....................................................... 287
Asynchronous Serial Interface Configuration ........................................................................................ 289
Relation between 5-Bit Counter Source Clock and m Value.................................................................. 302
Relation between Main System Clock and Baud Rate .......................................................................... 303