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參數(shù)資料
| 型號： | μPD45128441 |
| 廠商： | NEC Corp. |
| 英文描述： | 128M-bit Synchronous DRAM(128M 同步DRAM) |
| 中文描述： | 128兆位同步DRAM（128M的同步DRAM）的 |
| 文件頁數(shù)： | 9/84頁 |
| 文件大?。?/td> | 693K |
| 代理商： | ΜPD45128441 |
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Preliminary Data Sheet
9
μ
PD45128441, 45128841, 45128163
13. Electrical Specifications .................................................................................................................. 34
13.1
AC Parameters for Read Timing ......................................................................................................... 39
13.2
AC Parameters for Write Timing ......................................................................................................... 41
13.3
Relationship between Frequency and Latency .................................................................................. 42
13.4
Mode Register Write ............................................................................................................................. 43
13.5
Power on Sequence and Auto Refresh .............................................................................................. 44
13.6
/CS Function ......................................................................................................................................... 45
13.7
Clock Suspension during Burst Read (using CKE Function) .......................................................... 46
13.8
Clock Suspension during Burst Write (using CKE Function) .......................................................... 48
13.9
Power Down Mode and Clock Mask ................................................................................................... 50
13.10 CBR Refresh ......................................................................................................................................... 51
13.11 Self Refresh (Entry and Exit) ............................................................................................................... 52
13.12 Random Column Read (Page with Same Bank) ................................................................................ 53
13.13 Random Column Write (Page with Same Bank) ................................................................................ 55
13.14 Random Row Read (Ping-Pong Banks) ............................................................................................. 57
13.15 Random Row Write (Ping-Pong Banks) ............................................................................................. 59
13.16 Read and Write ..................................................................................................................................... 61
13.17 Interleaved Column Read Cycle .......................................................................................................... 63
13.18 Interleaved Column Write Cycle .......................................................................................................... 65
13.19 Auto Precharge after Read Burst ........................................................................................................ 67
13.20 Auto Precharge after Write Burst ........................................................................................................ 69
13.21 Full Page Read Cycle ........................................................................................................................... 71
13.22 Full Page Write Cycle ........................................................................................................................... 73
13.23 Byte Write Operation ............................................................................................................................ 75
13.24 Burst Read and Single Write (Option) ................................................................................................ 76
13.25 Full Page Random Column Read ........................................................................................................ 77
13.26 Full Page Random Column Write ........................................................................................................ 78
13.27 PRE (Precharge) Termination of Burst ............................................................................................... 79
14. Package Drawing ............................................................................................................................. 81
15. Recommended Soldering Conditions ............................................................................................ 82
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PD45128441G5 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range) |
| PD45128441G5-A10I-9JF | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range) |
| PD45128441G5-A10LI-9JF | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range) |
| PD45128441G5-A10LT-9JF | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range) |
| PD45128441G5-A10T-9JF | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range) |
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