參數(shù)資料
型號(hào): μPD4516161A
廠商: NEC Corp.
英文描述: 16M-bit Synchronous DRAM(16M 同步動(dòng)態(tài)RAM)
中文描述: 1,600位同步DRAM(1,600同步動(dòng)態(tài)RAM)的
文件頁(yè)數(shù): 1/86頁(yè)
文件大小: 904K
代理商: ΜPD4516161A
MOS INTEGRATED CIRCUIT
μ
PD4516421A, 4516821A, 4516161A for Rev. P
16M-bit Synchronous DRAM
The information in this document is subject to change without notice.
Description
The
μ
PD4516421A, 4516821A, 4516161A are high-speed 16,777,216-bit synchronous dynamic random-access
memories, organized as 2,097,152
×
4
×
2, 1,048,576
×
8
×
2 and 524,288
×
16
×
2 (word
×
bit
×
bank), respectively.
The synchronous DRAMs achieve high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
The synchronous DRAMs are packaged in 44-pin TSOP (II) (
×
4,
×
8) and 50-pin TSOP (II) (
×
16).
Features
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
Pulsed interface
Possible to assert random column address in every cycle
Dual internal banks controlled by A11 (Bank Select)
Programmable burst-length (1, 2, 4, 8, Full Page)
Programmable wrap sequence (Sequential/Interleave)
Programmable CAS latency (2, 3)
Automatic precharge and controlled precharge
CBR (Auto) refresh and self refresh
×
4,
×
8,
×
16 organization
Single + 3.3
±
0.3 V power supply
LVTTL compatible
Byte control (
×
16) by LDQM and UDQM
2,048 refresh cycles/32 ms
Burst termination by Burst Stop command and Precharge command
The mark shows major revised points.
1997
DATA SHEET
Document No. M12939EJ3V0DS00 (3rd edition)
Date Published April 1998 N CP(K)
Printed in Japan
相關(guān)PDF資料
PDF描述
μPD4516421A 16M-bit Synchronous DRAM(16M 同步動(dòng)態(tài)RAM)
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