參數(shù)資料
型號(hào)： μPD45256163
廠商： NEC Corp.
英文描述： 256M-Bit Synchronous DRAM(256M 同步 動(dòng)態(tài)RAM)
中文描述： 256M位同步DRAM（256M同步動(dòng)態(tài)RAM）的
文件頁(yè)數(shù)： 1/84頁(yè)
文件大?。?/td> 1052K
代理商： ΜPD45256163
MOS INTEGRATED CIRCUIT
μ
PD45256441,45256841,45256163
256M-bit Synchronous DRAM
4-bank, LVTTL
Document No.
Date Published
Printed in Japan
M13394EJ1V0DS00 (1st edition)
March 1998 NS CP(K)
PRELIMINARY DATA SHEET
NEC Corporation 1998
The information in this document is subject to change without notice.
Description
The
μ
PD45256441, 45256841, 45256163 are high-speed 268,435,456 bit synchronous dynamic random-access
memories, organized as 16,777,216x4x4, 8,388,608x8x4, 4,194,304x16x4 (word x bit x bank), respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
These products are packaged in 54-pin TSOP (II).
Features
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
Pulsed interface
Possible to assert random column address in every cycle
Quad internal banks controlled by BA0 and BA1(Bank Select)
Byte control (x16) by LDQM and UDQM
Programmable Wrap sequence (Sequential / Interleave)
Programmable burst length (1, 2, 4, 8 and full page)
Programmable /CAS latency (2 and 3)
Automatic precharge and controlled precharge
CBR (Auto) refresh and self refresh
x4, x8, x16 organization
Single 3.3 V
±
0.3 V power supply
LVTTL compatible inputs and outputs
8,192 refresh cycles/64 ms
Burst termination by Burst stop command and Precharge command
相關(guān)PDF資料
PDF描述
μPD45256441 256M-Bit Synchronous DRAM(256M 同步 動(dòng)態(tài)RAM)
μPD45256841 256M-Bit Synchronous DRAM(256M 同步 動(dòng)態(tài)RAM)
μPD4564163 64M-bit Synchronous DRAM(64M同步動(dòng)態(tài)RAM)
μPD4564441 64M-bit Synchronous DRAM(64M同步動(dòng)態(tài)RAM)
μPD4564841 64M-bit Synchronous DRAM(64M同步動(dòng)態(tài)RAM)
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