參數(shù)資料
型號: μPD45128441
廠商: NEC Corp.
英文描述: 128M-bit Synchronous DRAM(128M 同步DRAM)
中文描述: 128兆位同步DRAM(128M的同步DRAM)的
文件頁數(shù): 20/84頁
文件大小: 693K
代理商: ΜPD45128441
Preliminary Data Sheet
20
μ
PD45128441, 45128841, 45128163
5. Initialization
The synchronous DRAM is initialized in the power-on sequence according to the following.
(1)
To stabilize internal circuits, when power is applied, a 100
μ
s or longer pause must precede any signal toggling.
(2)
After the pause, both banks must be precharged using the Precharge command (The Precharge all banks
command is convenient).
(3)
Once the precharge is completed and the minimum t
RP
is satisfied, the mode register can be programmed.
After the mode register set cycle, t
RSC
(2 CLK minimum) pause must be satisfied as well.
(4)
Two or more CBR (Auto) refresh must be performed.
Remarks 1.
The sequence of Mode register programming and Refresh above may be transposed.
2.
CKE and DQM must be held high until the Precharge command is issued to ensure data-bus Hi-Z.
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