UM001600-Z8X0599
7-1
U
SER
’
S
M
ANUAL
C
HAPTER
7
I
NTERRUPTS
7.1 INTRODUCTION
The Z8 MCU
allows 6 different interrupts from a variety of
sources; up to four external inputs, the on-chip
Counter/Timer(s), software, and serial I/O peripherals.
These interrupts can be masked and their priorities set by
using the Interrupt Mask and the Interrupt Priority Regis-
ters. All six interrupts can be globally disabled by resetting
the master Interrupt Enable, bit 7 in the Interrupt Mask
Register, with a Disable Interrupt (DI) instruction. Interrupts
are globally enabled by setting bit 7 with an Enable Inter-
rupt (EI) instruction.
There are three interrupt control registers: the Interrupt Re-
quest Register (IRQ), the Interrupt Mask register (IMR),
and the Interrupt Priority Register (IPR). Figure 7-1 shows
addresses and identifiers for the interrupt control registers.
Figure 7-2 is a block diagram showing the Interrupt Mask
and Interrupt Priority logic.
The Z8 MCU family supports both vectored and polled in-
terrupt handling. Details on vectored and polled interrupts
can be found later in this chapter.
Note:
See the selected Z8 MCU's product specification
for the exact interrupt sources supported.
Figure 7-1. Interrupt Control Registers
Register
HEX
Interrupt Mask
Interrupt Request
Interrupt Priority
Identifier
FBH
FAH
F9H
IMR
IRQ
IPR
Figure 7-2. Interrupt Block Diagram
IRQ
IRQ
0
- IRQ
5
Vector Select
Interrupt
Request
IMR
IPR
Priority Logic
6
Global
Interrupt
Enable
6