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| 型號(hào)： | Z80B-PIO |
| 英文描述： | Z8 Microcontrollers |
| 中文描述： | Z8微控制器 |
| 文件頁(yè)數(shù)： | 104/222頁(yè) |
| 文件大小： | 1595K |
| 代理商： | Z80B-PIO |
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Z8 Microcontrollers
Power-Down Modes
ZiLOG
8-2
UM001600-Z8X0599
8.3 STOP MODE OPERATION
The STOP mode provides the lowest possible device
standby current. This instruction turns off the on-chip oscil-
lator and internal system clock.
To enter the STOP mode, it is necessary to first flush the
instruction pipeline to avoid suspending execution in mid-
instruction. To do this, the application program must exe-
cute a NOP instruction (opcode=FFH) immediately before
the STOP instruction (opcode=6FH), that is,
The STOP mode is exited by any one of the following re-
sets: Power-On Reset activation, WDT time out (if avail-
able), or a STOP-Mode Recovery source. Upon reset gen-
eration, the processor will always restart the application
program at address 000CH.
POR/RESET activation is present on all Z8 devices and is
implemented as a reset pin and/or an on-chip power on re-
set circuit.
Some Z8 devices allow for the on-chip WDT to run in the
STOP mode. If so activated, the WDT timeout will gener-
ate a reset some fixed time period after entering the STOP
mode.
Note:
STOP-Mode Recovery by the WDT will increase
the STOP mode standby current (I
CC2
). This is due to the
WDT clock and divider circuitry that is now enabled and
running to support this recovery mode. See the product
data sheet for actual I
CC2
values.
All Z8 devices provide some form of dedicated STOP-
Mode Recovery (SMR) circuitry. Two SMR methods are
implemented — a single fixed input pin or a flexible, pro-
grammable set of inputs. The selected Z8 device product
specification should be reviewed to determine the SMR
options available for use.
Note:
For devices that support SPI, the slave mode
compare feature also serves as a SMR source.
In the simple case, a low level applied to input pin P27 will
trigger a SMR. To use this mode, pin P27 (I/O Port 2, bit 7)
must be configured as an input before the STOP mode is
entered. The low level on P27 must meet a minimum pulse
width T
WSM
. (See the product data sheet) to trigger the de-
vice reset mode). Some Z8 devices provide multiple SMR
input sources. The desired SMR source is selected via the
SMR Register.
Note:
Use of specialized SMR modes (P2.7 input or
SMR register based) or the WDT timeout (only when in the
STOP mode) provide a unique reset operation. Some
control registers are initialized differently for a SMR/WDT
triggered POR than a standard reset operation. See the
product specification (register file map) for exact details.
To determine the actual STOP mode current (I
CC2
) value
for the optional SMR modes available, see the selected Z8
device’s product data sheet.
Note:
The STOP mode current (I
CC2
) will be minimized
when:
V
CC
is at the low end of the devices operating range.
WDT is off in the STOP mode.
Output current sourcing is minimized.
All inputs (digital and analog) are at the low or high rail
voltages.
FF
6F
NOP
STOP
;clear the instruction pipeline
;enter STOP mode
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