UM001600-Z8X0599
4-1
U
SER
’
S
M
ANUAL
C
HAPTER
4
R
ESET
—W
ATCH
-D
OG
T
IMER
4.1 RESET
This section describes the Z8 MCU
reset conditions, reset
timing, and register initialization procedures. Reset is gen-
erated by Power-On Reset (POR), Reset Pin, Watch-Dog
Timer (WDT), and Stop-Mode Recovery.
A system reset overrides all other operating conditions and
puts the Z8 into a known state. To initialize the chip’s inter-
nal logic, the
RESET
input must be held Low for at least 21
SCP or 5 XTAL clock cycles. The control register and ports
are reset to their default conditions after a POR, a reset
from the
RESET
pin, or Watch-Dog Timer timeout while in
RUN mode and HALT mode. The control registers and
ports are not reset to their default conditions after Stop-
Mode Recovery and WDT timeout while in STOP mode.
While
RESET
pin is Low,
AS
is output at the internal clock
rate,
DS
is forced Low, and R//W remains High. The pro-
gram counter is loaded with 000CH. I/O ports and control
registers are configured to their default reset state.
Resetting the Z8 does not effect the contents of the
general-purpose registers.
4.2 RESET PIN, INTERNAL POR OPERATION
In some cases, the Z8 hardware
RESET
pin initializes the
control and peripheral registers, as shown in Tables 4-1, 4-
2, 4-3, and 4-4. Specific reset values are shown by 1 or 0,
while bits whose states are unknown are indicated by the
letter U. The Tables 4-1, 4-2, 4-3, and 4-4 show the reset
conditions for the generic Z8.
Note:
The register file reset state is device dependent.
Please refer to the selected device product specifications
for register availability and reset state.