
XRT94L43
306
REV. 1.0.2
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
4.3
Ingress Timing for STS-1/STM-0 Applications
Table 11 presents information on the Timing parameters for the DS3/E3/STS-1 LIU Interface Signals (in the
Ingress Direction) for STS-1/STM-0 Applications.
4.4
The Egress DS3/E3/STS-1 Interface Timing
The user should be aware of the followings things about the Egress DS3/E3/STS-1 Interface timing.
a. If a given channel is configured to operate in the DS3/E3 Mode, then the DS3/E3 Framer block can be
configured to output the outbound DS3/E3 data (via the DS3/E3/STS_1_DATA_OUT and DS3/E3/
STS_1_NEG_OUT output pins) upon either the rising or falling edge of DS3/E3/STS_1_CLOCK_OUT.
b. If a given channel is configured to operate in the STS-1/STM-0 Mode, then the Transmit STS-1 TOH
Processor block will be operating in the Single-Rail Mode (e.g., the Transmit STS-1 TOH Processor
block will output all outbound STS-1/STM-0 data via the DS3/E3/STS_1_DATA_OUT output pin. No
data will be output via the DS3/E3/STS_1_NEG_OUT output pin).
c. Further, if a given channel is configured to operate in the STS-1/STM-0 Mode, then the Transmit STS-1
TOH Processor block can ONLY be configured to output the outbound STS-1/STM-0 data (via the DS3/
E3/STS_1_DATA_OUT pin) upon the rising edge of DS3/E3/STS_1_CLOCK_OUT.
TABLE 10: TIMING INFORMATION FOR THE INGRESS DS3/E3/STS-1 LIU INTERFACE FOR DS3/E3 APPLICATIONS
AND WHEN THE
DS3/E3 FRAMER BLOCK HAS BEEN CONFIGURED TO SAMPLE THE DS3/E3/STS_1_DATA_IN AND
DS3/E3/STS_1_NEG_IN INPUT PINS UPON THE FALLING EDGE OF DS3/E3/STS_1_CLOCK_IN
SYMBOL
DESCRIPTION
MIN.
TYP.
MAX.
t9
DS3/E3/STS_1_DATA_IN and DS3/E3/STS_1_NEG_IN to
falling edge of DS3/E3/STS_1_CLOCK_IN set-up time
requirements
7ns
t10
Falling edge of DS3/E3/STS_1_CLOCK_IN to DS3/E3/
STS_1_DATA_IN and DS3/E3/STS_1_NEG_IN Hold time
requirements
0ns
TABLE 11: TIMING INFORMATION FOR THE INGRESS DS3/E3/STS-1 LIU INTERFACE FOR STS-1/STM-0
APPLICATIONS
SYMBOL
DESCRIPTION
MIN.
TYP.
MAX.
t9
DS3/E3/STS_1_DATA_IN to rising edge of DS3/E3/
STS_1_CLOCK_IN set-up time requirements
4ns
t10
Rising edge of DS3/E3/STS_1_CLK_IN to DS3/E3/
STS_1_DATA_IN and DS3/E3/STS_1_CLOCK_IN
Hold time requirements
0ns