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XRT94L43
295
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
REV. 1.0.2
NOTE: The values for t0 through t7 can be found in Table 2. NOTE: Test Conditions: TA = 25°C, VCC = 3.3V±5% and 2.5V±5%, unless otherwise specified.
FIGURE 8. ASYNCHRONOUS MODE 2 - MOTOROLA 68K PROGRAMMED I/O TIMING (READ CYCLE)
TABLE 2: TIMING INFORMATION FOR THE MICROPROCESSOR INTERFACE WHEN CONFIGURED TO OPERATE IN THE
MOTOROLA (68K) ASYNCHRONOUS MODE
TIMING
DESCRIPTION
MIN.
TYP.
MAX
t0
Address setup time to pALE low
6
-
t1
Address hold time to pALE high
6
-
t2
Data setup time to pDS_L low
0
-
t3
Data hold time to pDS_L low
160
-
t4
pDS_L high to pRDY_L high (Write Cycle)
-
16
t5
pRDY_L low to Data valid
-
15
t6
pDS_L high to pRDY_L high (Read Cycle)
-
16
t7
pRDY_L high to Data invalid
3
-
Data
CS
ALE_AS
A[6:0]
D[7:0]
RD_DS
WR_R/W
RDY_DTACK
t
6
t
7
Address
t
0
t
1
t
5