S
參數(shù)資料
型號： XRT86VX38IB329-F
廠商： Exar Corporation
文件頁數(shù)： 8/61頁
文件大?。?/td> 0K
描述： IC TI/E1/J1 FRAMER/LIU 329FPBGA
標準包裝： 90
控制器類型： T1/E1/J1 調幀器，LIU
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 329-FBGA
供應商設備封裝： 329-FPBGA（17x17）
包裝： 散裝
其它名稱： 1016-1439
XRT86VX38
13
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.3
TRANSMIT SYSTEM SIDE INTERFACE
SIGNAL NAME
329 PKG
BALL#
256 PKG
BALL #
TYPE
OUTPUT
DRIVE(MA)
DESCRIPTION
TxSER0/
TxPOS0
TxSER1/
TxPOS1
TxSER2/
TxPOS2
TxSER3/
TxPOS3
TxSER4/
TxPOS4
TxSER5/
TxPOS5
TxSER6/
TxPOS6
TxSER7/
TxPOS7
D11
A14
D17
F19
W17
V13
W9
W6
E10
C12
D14
F15
N12
P10
T8
P5
I-
Transmit Serial Data Input (TxSERn)/Transmit Positive
Digital Input (TxPOSn):
The exact function of these pins depends on the mode of
operation selected, as described below.
DS1/E1 Mode - TxSERn
These pins function as the transmit serial data input on the
system side interface, which are latched on the rising edge of
the TxSERCLKn pin. Any payload data applied to this pin will
be inserted into an outbound DS1/E1 frame and output to the
line. In DS1 mode, the framing alignment bits, facility data link
bits, CRC-6 bits, and signaling information can also be
inserted from this input pin if configured appropriately. In E1
mode, all data intended to be transported via Time Slots 1
through 15 and Time slots 17 through 31 must be applied to
this input pin. Data intended for Time Slots 0 and 16 can also
be applied to this input pin If configured accordingly.
DS1 or E1 High-Speed Multiplexed Mode* - TxSERn
In this mode, these pins are used as the high-speed multi-
plexed data input pin on the system side. High-speed multi-
plexed data of channels 0-3 must be applied to TxSER0 and
high-speed multiplexed data of channels 4-7 must be applied
to TxSER4 in a byte or bit-interleaved way. The framer latches
in the multiplexed data on TxSER0 and TxSER4 using TxM-
SYNC/TxINCLK and demultiplexes this data into 4 serial
streams. The LIU block will then output the data to the line
interface using TxSERCLKn.
DS1 or E1 Framer Bypass Mode - TxPOSn
In this mode, TxSERn is used for the positive digital input pin
(TxPOSn) to the LIU.
NOTE:
1.
*High-speed multiplexed modes include (For T1/E1)
16.384MHz HMVIP, H.100, Bit-multiplexed modes,
and (For T1 only) 12.352MHz Bit-multiplexed mode.
2.
In DS1 high-speed modes, the DS-0 data is mapped
into an E1 frame by ignoring every fourth time slot
(don’t care).
3.
These 8 pins are internally pulled “High” for each
channel.
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