參數(shù)資料
型號(hào)： XRT86VX38IB329-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 29/61頁(yè)
文件大?。?/td> 0K
描述： IC TI/E1/J1 FRAMER/LIU 329FPBGA
標(biāo)準(zhǔn)包裝： 90
控制器類(lèi)型： T1/E1/J1 調(diào)幀器，LIU
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 329-FBGA
供應(yīng)商設(shè)備封裝： 329-FPBGA（17x17）
包裝： 散裝
其它名稱(chēng)： 1016-1439
XRT86VX38
32
REV. 1.0.3
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
RD/DS/WE
N17
L15
I
-
Microprocessor Interface—Read Strobe Input:
The exact behavior of this pin depends upon the type of
Microprocessor/Microcontroller the Framer has been con-
figured to operate in, as defined by the PTYPE[2:0] pins.
Intel-Asynchronous Mode - RD - READ Strobe Input:
This input pin will function as the RD (Active Low Read
Strobe) input signal from the Microprocessor. Once this
active-low signal is asserted, then the XRT86VX38 device
will place the contents of the addressed register (or buffer
location) on the
Microprocessor Interface Bi-directional data bus (D[7:0]).
When this signal is negated, then the Data Bus will be tri-
stated.
Motorola-Asynchronous (68K) Mode - DS - Data
Strobe:
This input pin will function as the DS (Data Strobe) input
signal.
Power PC 403 Mode - WE - Write Enable Input:
This input pin will function as the WE (Write Enable) input
pin.
Anytime the Microprocessor Interface samples this active-
low input signal (along with CS and WR/R/W) also being
asserted (at a logic low level) upon the rising edge of
PCLK, then the Microprocessor Interface will (upon the
very same rising edge of PCLK) latch the
contents on the Bi-Directional Data Bus (D[7:0]) into the
“target” on-chip register or buffer location within the
XRT86VX38 device.
WR / R/W
G17
F13
I
-
Microprocessor Interface—Write Strobe Input
The exact behavior of this pin depends upon the type of
Microprocessor/Microcontroller the XRT86VX38 has been
configured to operate in, as defined by the PTYPE[2:0]
pins.
Intel-Asynchronous Mode - WR - Write Strobe Input:
This input pin functions as the WR (Active Low WRITE
Strobe) input signal from the Microprocessor. Once this
active-low signal is asserted, then the input buffers (associ-
ated with the Bi-Directional Data Bus pin, D[7:0]) will be
enabled.
The Microprocessor Interface will latch the contents on the
Bi-Directional Data Bus (into the “target” register or
address location, within the XRT86VX38) upon the rising
edge of this input pin.
Motorola-Asynchronous Mode - R/W - Read/Write
Operation Identification Input Pin:
This pin is functionally equivalent to the “R/W” input pin. In
the Motorola Mode, a “READ” operation occurs if this pin is
held at a logic “1”, coincident to a falling edge of the RD/DS
(Data Strobe) input pin. Similarly a WRITE operation
occurs if this pin is at a logic “0”, coincident to a falling edge
of the RD/DS (Data Strobe) input pin.
MICROPROCESSOR INTERFACE
SIGNAL NAME
329 PKG
BALL#
256 PKG
BALL #
TYPE
OUTPUT
DRIVE (MA)
DESCRIPTION
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