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參數(shù)資料
型號(hào)： XRT86VX38IB329-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 19/61頁(yè)
文件大小： 0K
描述： IC TI/E1/J1 FRAMER/LIU 329FPBGA
標(biāo)準(zhǔn)包裝： 90
控制器類型： T1/E1/J1 調(diào)幀器，LIU
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 329-FBGA
供應(yīng)商設(shè)備封裝： 329-FPBGA（17x17）
包裝： 散裝
其它名稱： 1016-1439
XRT86VX38
23
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.3
RECEIVE LINE INTERFACE
SIGNAL NAME
329 PKG
BALL#
256 PKG
BALL #
TYPE
OUTPUT
DRIVE (MA)
DESCRIPTION
RTIP0
RTIP1
RTIP2
RTIP3
RTIP4
RTIP5
RTIP6
RTIP7
C1
E1
H1
K1
M1
P1
T1
W2
B1
D1
F1
H1
K1
M1
P1
T2
I-
Receive Positive Analog Input (RTIPn):
RTIP is the positive differential input from the line inter-
face. This input pin, along with the RRING input pin, func-
tions as the “Receive DS1/E1 Line Signal” input for the
XRT86VX38 device.
The user is expected to connect this signal and the
RRING input signal to a 1:1 transformer for proper opera-
tion. The center tap of the receive transformer should have
a bypass capacitor of 0.1
F to ground (Chip Side) to
improve long haul application receive capabilities.
RRING0
RRING1
RRING2
RRING3
RRING4
RRING5
RRING6
RRING7
D1
F1
J1
L1
N1
R1
U1
W3
C1
E1
G1
J1
L1
N1
R1
T3
I-
Receive Negative Analog Input (RRINGn):
RRING is the negative differential input from the line inter-
face. This input pin, along with the RTIP input pin, func-
tions as the “Receive DS1/E1 Line Signal” input for the
XRT86VX38 device.
The user is expected to connect this signal and the RTIP
input signal to a 1:1 transformer for proper operation. The
center tap of the receive transformer should have a
bypass capacitor of 0.1
F to ground (Chip Side) to
improve long haul application receive capabilities.
RxLOS0
RxLOS1
RxLOS2
RxLOS3
RxLOS4
RxLOS5
RxLOS6
RxLOS7
B8
B13
D15
E18
U19
U15
V11
V7
A7
C11
F11
D16
P16
P12
R10
P7
O4
Receive Loss of Signal Output Indicator (RLOSn):
The XRT86VX38 device will assert this output pin (i.e.,
toggle it “high”) anytime (and for the duration that) the
Receive DS1/E1 Framer or LIU block declares the LOS
defect condition.
Conversely, the XRT86VX38 will "TRI-State" this pin any-
time (and for the duration that) the Receive DS1/E1
Framer or LIU block is NOT declaring the LOS defect con-
dition.
NOTE: Since the XRT86VX38 tri-states this output pin
(anytime the channel is not declaring the LOS
defect condition), the user MUST connect a "pull-
down" resistor (ranging from 1K to 10K) to each
RxLOS output pin, to pull this output pin to the
logic "LOW" condition, whenever the Channel is
NOT declaring the LOS defect condition.
This output pin will toggle “High” (declare LOS) if the
Receive Framer or the Receive LIU block associated with
Channel N determines that an RLOS condition occurs. In
other words, this pin is OR-ed with the LIU RLOS and the
Framer RLOS bit. If either the LIU RLOS or the Framer
RLOS bit associated with channel N pulses high, the cor-
responding RLOS pin of that particular channel will be set
to “High”.
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