參數(shù)資料
型號(hào)： XRT86VX38IB329-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 10/61頁(yè)
文件大小： 0K
描述： IC TI/E1/J1 FRAMER/LIU 329FPBGA
標(biāo)準(zhǔn)包裝： 90
控制器類型： T1/E1/J1 調(diào)幀器，LIU
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 329-FBGA
供應(yīng)商設(shè)備封裝： 329-FPBGA（17x17）
包裝： 散裝
其它名稱： 1016-1439
XRT86VX38
15
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.3
TxSYNC0/
TxNEG0
TxSYNC1/
TxNEG1
TxSYNC2/
TxNEG2
TxSYNC3/
TxNEG3
TxSYNC4/
TxNEG4
TxSYNC5/
TxNEG5
TxSYNC6/
TxNEG6
TxSYNC7/
TxNEG7
A9
A13
D16
E19
T16
U13
V9
W7
C9
B12
A14
E15
T13
M11
N8
T6
I/O
12
Transmit Single Frame Sync Pulse (TxSYNCn) / Transmit
Negative Digital Input (TxNEGn):
The exact function of these pins depends on the mode of
operation selected, as described below.
DS1/E1 Base Rate Mode (1.544MHz/2.048MHz) - TxSYNCn:
These TxSYNCn pins are used to indicate the single frame
boundary within an outbound T1/E1 frame. In both DS1 or E1
mode, the single frame boundary repeats every 125 microsec-
onds (8kHz).
In DS1/E1 base rate, TxSYNCn can be configured as either
input or output as described below.
When TxSYNCn is configured as an Input:
Users must provide a signal which must pulse "High" for one
period of TxSERCLK during the first bit of an outbound DS1/
E1 frame. It is imperative that the TxSYNC input signal be syn-
chronized with the TxSERCLK input signal.
When TxSYNCn is configured as an Output:
The transmit T1/E1 framer will output a signal which pulses
"High" for one period of TxSERCLK during the first bit of an
outbound DS1/E1 frame.
DS1/E1 High-Speed Backplane Modes* - TxSYNCn as
INPUT ONLY:
In this mode, TxSYNCn must be an input regardless of the
clock source that is chosen to be the timing source for the
transmit framer. In 2.048MVIP/4.096/8.192MHz high-speed
modes, TxSYNCn pins must be pulsed ’High’ for one period of
TxSERCLK during the first bit of the outbound T1/E1 frame. In
HMVIP mode, TxSYNC0 and TxSYNC4 must be pulsed ’High’
for 4 clock cycles of the TxMSYNC/TxINCLK signal in the
position of the first two and the last two bits of a multiplexed
frame. In H.100 mode, TxSYNC0 and TxSYNC4 must be
pulsed ’High’ for 2 clock cycles of the TxMSYNC/TxINCLK sig-
nal in the position of the first and the last bit of a multiplexed
frame.
DS1 or E1 Framer Bypass Mode - TxNEGn
In this mode, TxSYNCn is used as the negative digital input
pin (TxNEG) to the LIU.
NOTE:
*High-speed backplane modes include (For T1/E1)
2.048MVIP,
4.096MHz,
8.192MHz,
16.384MHz
HMVIP, H.100, Bit-multiplexed modes, and (For T1
only) 12.352MHz Bit-multiplexed mode.
NOTE: In DS1 high-speed modes, the DS-0 data is mapped
into an E1 frame by ignoring every fourth time slot
(don’t care).
NOTE:
These 8 pins are internally pulled “Low” for each
channel.
TRANSMIT SYSTEM SIDE INTERFACE
SIGNAL NAME
329 PKG
BALL#
256 PKG
BALL #
TYPE
OUTPUT
DRIVE(MA)
DESCRIPTION
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