
XRT84L38
410
OCTAL T1/E1/J1 FRAMER
REV. 1.0.1
There are two 96-byte receive message buffer in shared memory for each of the eight framers to receive data
link information. When one message buffer is filled up, the DS1 Receive HDLC Controller automatically
switches to the next message buffer to store data link messages. These two message buffers ping-pong
among each other for data link message storage.
The SLC96 Enable bit and the Message Type bit of the Data Link Status Register (DLSR) determines which
one of the three messages is received and processed by the Receive HDLC Controller block.
The table below shows configuration of the SLC96 Enable bit of the Data Link Control Register (DLCR).
DATA LINK CONTROL REGISTER (DLCR) (INDIRECT ADDRESS = 0XN0H, 0X13H)
The table below shows configuration of the Message Type bit of the Data Link Status Register (DLSR).
DATA LINK STATUS REGISTER (DLSR) (INDIRECT ADDRESS = 0XNAH, 0X06H)
13.2.2
How to configure XRT84L38 to Receive data link information through D or E Channels
The XRT84L38 can configure any one or ones of the twenty-four DS0 channels to be D or E channels. D
channel is used primarily for data link applications. E channel is used primarily for signaling for circuit switching
with multiple access configurations.
The Receive Conditioning Select [3:0] bits of the Receive Channel Control Register (RCCR) of each channel
determine whether that particular channel is configured as D or E channel. These bits also determine what
type of data or signaling conditioning is applied to each channel.
RECEIVE CHANNEL CONTROL REGISTER (RCCR) (INDIRECT ADDRESS = 0XN2H, 0X60H - 0X7FH)
If the Receive Conditioning Select [3:0] bits of the Receive Channel Control Register of a particular timeslot are
set to 1111, that timeslot is configured as a D or E timeslot.
Any D or E timeslot can be configured to direct data link information to the following destinations:
DS1 Receive Overhead Output Interface Block
DS1 Receive HDLC Controller Block
DS1 Receive Serial Output Interface Block
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
7
SLC96 Enable
R/W
0 - In SLC96 framing mode, the data link transmission is disabled. The
framer receives the regular SF framing bits.
In ESF framing mode, the framer receives regular ESF framing bits and
Facility Data Link (FDL) bits.
1 - In SLC96 framing mode, the data link transmission is enabled.
In ESF framing mode, the framer receives SLC96-like message in the
Facility Data Link bits.
B
IT
N
UMBER
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
7
Message Type
RUR /
WC
0 - The Receive HDLC Controller receives and processes Bit-Oriented
Signaling (BOS) message.
1 - The Receive HDLC Controller receives and processes LAPD protocol
or Message-Oriented Signaling (MOS) message.
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
3-0
Receive Condition-
ing Select
R/W
1111 - This channel is configured as D or E timeslot.