
XRT84L38
391
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER
XRT84L38 allows user to insert data link information to outbound DS1 frames. The data link information in
DS1raming format mode can be inserted from:
DS1 Transmit Overhead Input Interface Block
DS1 Transmit HDLC Controller
DS1 Transmit Serial Input Interface
The Transmit Data Link Source Select [1:0] bits, within the Transmit Data Link Select Register (TSDLSR)
determine source of the data link bits (Facility Data Link (FDL) bits in ESF framing format mode, Signaling
Framing (Fs) bits in SLC96 framing format mode and Remote Signaling (R) bits in T1DM framing format
mode) to be inserted into the outgoing DS1 frames.
The table below shows configuration of the Transmit Data Link Source Select [1:0] bits of the Transmit Data
Link Select Register (TSDLSR).
TRANSMIT DATA LINK SELECT REGISTER (TSDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0AH)
If the Transmit Data Link Source Select bits of the Transmit Data Link Select Register are set to 00, the
Transmit HDLC Controller block becomes input source of the data link bits in outgoing DS1 frames.
Each of the eight framers within the XRT84L38 device contains a DS1 Transmit High-level Data Link Controller
(HDLC) block. The function of this block is to provide a serial data link channel in DS1 mode through the
following:
Facility Data Link (FDL) bits in ESF framing format mode
Signaling Framing (Fs) bits in SLC96 framing format mode
Remote Signaling (R) bits in T1DM framing format mode
D or E signaling timeslot channel
Data link bits are automatically inserted into the Facility Data Link (FDL) bits in ESF framing format mode,
Signaling Framing (Fs) bits in SLC96 framing format mode and Remote Signaling (R) bits in T1DM framing
format mode or forced to 1 by the framer. Additionally, XRT84L38 allows the user to define any one of ones of
the twenty-four DS0 timeslots to be D or E channel. We will discuss how to configure XRT84L38 to transmit
data link information through D or E channels in later section.
The DS1 Transmit HDLC Controller block contains three major functional modules associated with DS1
framing formats. They are the:
SLC96 Data Link Controller
LAPD Controller
Bit-Oriented Signaling Processor.
There are two 96-byte transmit message buffers in shared memory for each of the eight framers to transmit
data link information. When one message buffer is filled up, the Transmit HDLC Controller automatically
switches to the next message buffer to load data link messages. These two message buffers ping-pong among
each other for data link message transmission.
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
1-0
Transmit Data
Link Source
Select [1:0]
R/W
00 - The data link bits are inserted into the framer through the Transmit HDLC
Controller.
01 - The data link bits are inserted into the framer through the Transmit Serial
Data input Interface via the TxSer_n pins.
10 - The data link bits are inserted into the framer through the Transmit Over-
head Input Interface via the TxOH_n pins.
11 - The data link bits are forced into 1.