
XRT84L38
287
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER
The table below shows the combinations of Receive Multiplex Enable bit and Receive Interface Mode Select
[1:0] bits and the resulting Receive Back-plane Interface data rates.
When the Receive Multiplex Enable bit is set to zero, the framer is configured in non-channel-multiplexed
mode. The possible data rates are XRT84V24 Compatible 2.048Mbit/s, MVIP 2.048Mbit/s, 4.096Mbit/s and
8.192Mbit/s. In non-channel-multiplexed mode, payload data of each channel are sending out from the
Receive High-speed Back-plane Interface separately. Each channel uses its own Receive Serial Clock,
Receive Serial Data, Receive Single-frame Synchronization signal and Receive Multi-frame Synchronization
signal as interface between the framer and the Terminal Equipment. Section 2.1.1.1, 2.1.1.2 and 2.1.1.3
provide details on how to connect the Receive Payload Data Interface block with the local Terminal Equipment
when the Back-plane interface data rate is 2.048Mbit/s.
When the Back-plane interface data rate is MVIP 2.048Mbit/s, 4.096Mbit/s and 8.192Mbit/s, the Receive Serial
Clock, Receive Serial Data and Receive Single-frame Synchronization are all configured as inputs. The
Receive Multi-frame Synchronization signal is still output. The Receive Serial Clock is configured as an input
timing source for the High-speed Back-plane Interface with frequencies of 2.048 MHz, 4.096 MHz and 8.192
MHz respectively.
The table below summaries the clock frequencies of RxSerClk_n input when the framer is operating in non-
multiplexed High-speed Back-plane mode.
RECEIVE MULTIPLEX ENABLE BIT = 0
When the Receive Multiplex Enable bit is set to one, the framer is configured in channel-multiplexed mode.
The possible data rates are bit-multiplexed 16.384Mbit/s, HMVIP 16.384Mbit/s and H.100 16.384Mbit/s. In
channel-multiplexed mode, four channels share the Receive Serial Data, Receive Single-frame
Synchronization signal and Receive Serial Clock of one channel as interface between the framer and the
Terminal Equipment. The Receive Serial Clock runs at frequencies of 12.352 MHz or 16.384 MHz. It serves as
the primary clock source for the High-speed Back-plane Interface.
Payload and signaling data of Channel 0-3 are multiplexed onto the Receive Serial Data pin of Channel 0.
Payload and signaling data of Channel 4-7 are multiplexed onto the Receive Serial Data pin of Channel 4. The
Receive Single-frame Synchronization signal of Channel 0 pulses HIGH at the beginning of the frame with data
R
ECEIVE
M
ULTIPLEX
E
NABLE
B
IT
R
ECEIVE
I
NTERFACE
M
ODE
S
ELECT
B
IT
1
R
ECEIVE
I
NTERFACE
M
ODE
S
ELECT
B
IT
0
B
ACK
-
PLANE
I
NTERFACE
D
ATA
R
ATE
0
0
0
XRT84V24 Compatible 2.048Mbit/s
0
0
1
MVIP 2.048Mbit/s
0
1
0
4.096Mbit/s
0
1
1
8.192Mbit/s
1
0
0
-
1
0
1
Bit Multiplexed 16.384Mbit/s
1
1
0
HMVIP 16.384Mbit/s
1
1
1
H.100 16.384Mbit/s
R
ECEIVE
I
NTERFACE
M
ODE
S
ELECT
B
IT
1
R
ECEIVE
I
NTERFACE
M
ODE
S
ELECT
B
IT
0
B
ACK
-
PLANE
I
NTERFACE
D
ATA
R
ATE
R
X
S
ER
C
LK
0
0
XRT84V24 Compatible 2.048Mbit/s
2.048MHz
0
1
MVIP 2.048Mbit/s
2.048 MHz
1
0
4.096Mbit/s
4.096 MHz
1
1
8.192Mbit/s
8.192 MHz