參數(shù)資料
型號： XE8000EV104
廠商： Semtech
文件頁數(shù)： 90/156頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR XE8805AMI028LF
標(biāo)準(zhǔn)包裝： 1
類型： MCU
適用于相關(guān)產(chǎn)品： XE88LC05AMI028
所含物品： 完全組裝的評估板
Semtech 2006
www.semtech.com
6-4
XE8805/05A
6.5
Reset source description
6.5.1
Power On Reset
The power on reset (POR) monitors the external supply voltage. It activates a reset on a rising edge of this supply
voltage. The reset is inactivated only if the internal voltage regulator has started up. No precise voltage level
detection is performed by the POR block.
6.5.2
RESET pin
The reset can be activated by applying a high input state on the RESET pin.
6.5.3
Programmable Port A input combination
A reset signal can be generated by Port A. See the description of the Port A for further information.
6.5.4
Watchdog reset
The Watchdog will generate a reset if the EnResetWD bit in the RegSysCtrl register has been set and if the
watchdog is not cleared in time by the processor. See chapter 6.7 describing the watchdog for further information.
6.5.5
BusError reset
The address space is assigned as shown in the register map of the product. If the EnBusError bit in the
RegSysCtrl register is set and a non-existant address is accessed by the software, a reset is generated.
6.5.6
Sleep mode
Entering the sleep mode will reset a part of the circuit. The reset is used to configure the circuit for correct wake-up
after the sleep mode. If the SleepEn bit in the RegSysCtrl register has been set, the sleep mode can be entered
by setting the bit Sleep in RegSysReset. During the sleep mode, the resetsleep signal is active. For detailed
information on the sleep mode, see the system documentation.
6.6
Control register description and operation
Two registers are dedicated for reset status and control, RegSysReset and RegSysCtrl. The bits Sleep, and
SleepEn are also located in those registers and are described in the chapter dedicated to the different operating
modes of the circuit (system block).
The RegSysReset register gives information on the source which generated the last reset. It can be read at the
beginning of the application program to detect if the circuit is recovering from an error or exception condition, or if
the circuit is starting up normally.
when ResBusError is 1, a forbidden address access generated the reset.
when ResWD is 1, the watchdog generated the reset.
when ResPortA is 1, a PortA combination generated the reset.
when ResPad is 1, a reset pin generated the reset.
when ResPadSleep is 1, a reset pin in sleep mode generated the reset.
Note: If no bit is set to 1, the reset source was the internal POR.
Note: Several bits might be set or not, if the register was not cleared in between 2 reset occurrences. Write
any value in RegSysReset to clear it.
Note: When a reset pin wakes up the chip from the sleep mode, ResPad and ResPadSleep bits are equal
at 1.
The last bit concerns the sleep mode control (see system documentation for the sleep mode description).
Not
Recommended
for
New
Designs
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