Dec reg C, V, Z, a a :=
參數(shù)資料
型號： XE8000EV104
廠商： Semtech
文件頁數(shù)： 72/156頁
文件大小： 0K
描述： EVAL BOARD FOR XE8805AMI028LF
標準包裝： 1
類型： MCU
適用于相關(guān)產(chǎn)品： XE88LC05AMI028
所含物品： 完全組裝的評估板
Semtech 2006
www.semtech.com
3-5
XE8805/05A
Dec reg
C, V, Z, a
a := reg-1; if a=hFF then C := 0 else C := 1; reg := a
Dec reg, eaddr
C, V, Z, a
a := DM(eaddr)-1; if a=hFF then C := 0 else C := 1; reg := a
Decc reg1, reg2
C, V, Z, a
a := reg2-(1-C); if a=hFF and C=0 then C := 0 else C := 1; reg1 := a
Decc reg
C, V, Z, a
a := reg-(1-C); if a=hFF and C=0 then C := 0 else C := 1; reg := a
Decc reg, eaddr
C, V, Z, a
a := DM(eaddr)-(1-C); if a=hFF and C=0 then C := 0 else C := 1; reg := a
And reg,#data[7:0]
-,-, Z, a
a := reg and data[7:0]; reg := a
And reg1, reg2, reg3
-,-, Z, a
a := reg2 and reg3; reg1 := a
And reg1, reg2
-,-, Z, a
a := reg1 and reg2; reg1 := a
And reg, eaddr
-,-, Z, a
a := reg and DM(eaddr); reg := a
Or reg,#data[7:0]
-,-, Z, a
a := reg or data[7:0]; reg := a
Or reg1, reg2, reg3
-,-, Z, a
a := reg2 or reg3; reg1 := a
Or reg1, reg2
-,-, Z, a
a := reg1 or reg2; reg1 := a
Or reg, eaddr
-,-, Z, a
a := reg or DM(eaddr); reg := a
Xor reg,#data[7:0]
-,-, Z, a
a := reg xor data[7:0]; reg := a
Xor reg1, reg2, reg3
-,-, Z, a
a := reg2 xor reg3; reg1 := a
Xor reg1, reg2
-,-, Z, a
a := reg1 xor reg2; reg1 := a
Xor reg, eaddr
-,-, Z, a
a := reg or DM(eaddr); reg := a
Add reg,#data[7:0]
C, V, Z, a
a := reg+data[7:0]; if overflow then C:=1 else C := 0; reg := a
Add reg1, reg2, reg3
C, V, Z, a
a := reg2+reg3; if overflow then C:=1 else C := 0; reg1 := a
Add reg1, reg2
C, V, Z, a
a := reg1+reg2; if overflow then C:=1 else C := 0; reg1 := a
Add reg, eaddr
C, V, Z, a
a := reg+DM(eaddr); if overflow then C:=1 else C := 0; reg := a
Addc reg,#data[7:0]
C, V, Z, a
a := reg+data[7:0]+C; if overflow then C:=1 else C := 0; reg := a
Addc reg1, reg2, reg3
C, V, Z, a
a := reg2+reg3+C; if overflow then C:=1 else C := 0; reg1 := a
Addc reg1, reg2
C, V, Z, a
a := reg1+reg2+C; if overflow then C:=1 else C := 0; reg1 := a
Addc reg, eaddr
C, V, Z, a
a := reg+DM(eaddr)+C; if overflow then C:=1 else C := 0; reg := a
Subd reg,#data[7:0]
C, V, Z, a
a := data[7:0]-reg; if underflow then C := 0 else C := 1; reg := a
Subd reg1, reg2, reg3
C, V, Z, a
a := reg2-reg3; if underflow then C := 0 else C := 1; reg1 := a
Subd reg1, reg2
C, V, Z, a
a := reg2-reg1; if underflow then C := 0 else C := 1; reg1 := a
Subd reg, eaddr
C, V, Z, a
a := DM(eaddr)-reg; if underflow then C := 0 else C := 1; reg := a
Subdc reg,#data[7:0]
C, V, Z, a
a := data[7:0]-reg-(1-C); if underflow then C := 0 else C := 1; reg := a
Subdc reg1, reg2, reg3
C, V, Z, a
a := reg2-reg3-(1-C); if underflow then C := 0 else C := 1; reg1 := a
Subdc reg1, reg2
C, V, Z, a
a := reg2-reg1-(1-C); if underflow then C := 0 else C := 1; reg1 := a
Subdc reg, eaddr
C, V, Z, a
a := DM(eaddr)-reg-(1-C); if underflow then C := 0 else C := 1; reg := a
Subs reg,#data[7:0]
C, V, Z, a
a := reg-data[7:0]; if underflow then C := 0 else C := 1; reg := a
Subs reg1, reg2, reg3
C, V, Z, a
a := reg3-reg2; if underflow then C := 0 else C := 1; reg1 := a
Subs reg1, reg2
C, V, Z, a
a := reg1-reg2; if underflow then C := 0 else C := 1; reg1 := a
Subs reg, eaddr
C, V, Z, a
a := reg-DM(eaddr); if underflow then C := 0 else C := 1; reg := a
Subsc reg,#data[7:0]
C, V, Z, a
a := reg-data[7:0]-(1-C); if underflow then C := 0 else C := 1; reg := a
Subsc reg1, reg2, reg3
C, V, Z, a
a := reg3-reg2-(1-C); if underflow then C := 0 else C := 1; reg1 := a
Subsc reg1, reg2
C, V, Z, a
a := reg1-reg2-(1-C); if underflow then C := 0 else C := 1; reg1 := a
Subsc reg, eaddr
C, V, Z, a
a := reg-DM(eaddr)-(1-C); if underflow then C := 0 else C := 1; reg := a
Mul reg,#data[7:0]
u, u, u, a
a := (data[7:0]*reg)[7:0]; reg := (data[7:0]*reg)[15:8]
Mul reg1, reg2, reg3
u, u, u, a
a := (reg2*reg3)[7:0]; reg1 := (reg2*reg3)[15:8]
Mul reg1, reg2
u, u, u, a
a := (reg2*reg1)[7:0]; reg1 := (reg2*reg1)[15:8]
Mul reg, eaddr
u, u, u, a
a := (DM(eaddr)*reg)[7:0]; reg := (DM(eaddr)*reg)[15:8]
Mula reg,#data[7:0]
u, u, u, a
a := (data[7:0]*reg)[7:0]; reg := (data[7:0]*reg)[15:8]
Mula reg1, reg2, reg3
u, u, u, a
a := (reg2*reg3)[7:0]; reg1 := (reg2*reg3)[15:8]
Mula reg1, reg2
u, u, u, a
a := (reg2*reg1)[7:0]; reg1 := (reg2*reg1)[15:8]
Mula reg, eaddr
u, u, u, a
a := (DM(eaddr)*reg)[7:0]; reg := (DM(eaddr)*reg)[15:8]
Mshl reg,#shift[2:0]
u, u, u, a
a := (reg*2
shift)[7:0]; reg := (reg*2shift)[15:8]
Mshr reg,#shift[2:0]
u, u, u, a
a := (reg*2
(8-shift)[7:0]; reg := (reg*2(8-shift)[15:8]
Mshra reg,#shift[2:0]
u, u, u, a*
a := (reg*2
(8-shift)[7:0]; reg := (reg*2(8-shift)[15:8]
Cmp reg,#data[7:0]
C, V, Z, a
a := data[7:0]-reg; if underflow then C :=0 else C:=1; V := C and (not Z)
Cmp reg1, reg2
C, V, Z, a
a := reg2-reg1; if underflow then C :=0 else C:=1; V := C and (not Z)
Cmp reg, eaddr
C, V, Z, a
a := DM(eaddr)-reg; if underflow then C :=0 else C:=1; V := C and (not Z)
Cmpa reg,#data[7:0]
C, V, Z, a
a := data[7:0]-reg; if underflow then C :=0 else C:=1; V := C and (not Z)
Cmpa reg1, reg2
C, V, Z, a
a := reg2-reg1; if underflow then C :=0 else C:=1; V := C and (not Z)
Cmpa reg, eaddr
C, V, Z, a
a := DM(eaddr)-reg; if underflow then C :=0 else C:=1; V := C and (not Z)
Tstb reg,#bit[2:0]
-, -, Z, a
a[bit] := reg[bit]; other bits in a are 0
Setb reg,#bit[2:0]
-, -, Z, a
reg[bit] := 1; other bits unchanged; a := reg
Clrb reg,#bit[2:0]
-, -, Z, a
reg[bit] := 0; other bits unchanged; a := reg
Invb reg,#bit[2:0]
-, -, Z, a
reg[bit] := not reg[bit]; other bits unchanged; a := reg
Not
Recommended
for
New
Designs
相關(guān)PDF資料
PDF描述
VE-B7P-EY CONVERTER MOD DC/DC 13.8V 50W
EBA28DRTH CONN EDGECARD .125 DIP 56POS
EEC20DRTH-S734 CONN EDGECARD 40POS DIP .100 SLD
AT-S-26-8/8/S-14-R MOD CORD STANDARD 8-8 SILVER 14'
EBC25DREN-S13 CONN EDGECARD 50POS .100 EXTEND
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