參數(shù)資料
型號： XE8000EV104
廠商： Semtech
文件頁數(shù)： 49/156頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR XE8805AMI028LF
標準包裝： 1
類型： MCU
適用于相關(guān)產(chǎn)品： XE88LC05AMI028
所含物品： 完全組裝的評估板
Semtech 2006
www.semtech.com
20-2
XE8805/05A
20.1
Features
4 x 8-bits timer/counter modules or 2 x 16-bits timers/counter modules
Each with 4 possible clock sources
Up/down counter modes
Interrupt and event generation
Capture function (internal or external source)
Rising, falling or both edge of capture signal
PA[3:0] can be used as clock inputs (debounced or direct)
2 x 8 bits PWM or 2 x 16 bits PWM
PWM resolution of 8, 10, 12, 14 or 16 bits
Complex mode combinations are possible between counter, capture and PWM modes
20.2
Overview
CounterA and CounterB are 8-bit counters and can be combined to form a 16-bit counter. CounterC and CounterD
exhibit the same features.
The counters can also be used to generate two PWM outputs on PB[0] and PB[1]. In PWM mode one can generate
PWM functions with 8, 10, 12, 14 or 16 bit wide counters.
The counters A and B can be captured by events on an internal or an external signal. The capture can be
performed on both 8-bit counters running individually on two different clock sources or on both counters chained to
form a 16-bit counter. In any case, the same capture signal is used for both counters.
When the counters A and B are not chained, they can be used in several configurations: A and B as counters, A
and B as captured counters, A as PWM and B as counter, A as PWM and B as captured counter.
When the counters C and D are not chained, they can be used either both as counters or counter C as PWM and
counter D as counter.
20.3
Register map
Bit
RegCntA
rw
reset
function
7-0
CounterA
r
xxxxxxxx
8-bits counter value
7-0
CounterA
w
xxxxxxxx
8-bits comparison value
Table 20-1. RegCntA
bit
RegCntB
rw
reset
function
7-0
CounterB
r
xxxxxxxx
8-bits counter value
7-0
CounterB
w
xxxxxxxx
8-bits comparison value
Table 20-2. RegCntB
Note: When writing to RegCntA or RegCntB, the processor writes the counter comparison values. When reading
these locations, the processor reads back either the actual counter value or the last captured value if the capture
mode is active.
bit
RegCntC
rw
reset
function
7-0
CounterC
r
xxxxxxxx
8-bits counter value
7-0
CounterC
w
xxxxxxxx
8-bits comparison value
Table 20-3. RegCntC
Not
Recommended
for
New
Designs
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