參數(shù)資料
型號： XE8000EV104
廠商： Semtech
文件頁數(shù)： 105/156頁
文件大小： 0K
描述： EVAL BOARD FOR XE8805AMI028LF
標(biāo)準(zhǔn)包裝： 1
類型： MCU
適用于相關(guān)產(chǎn)品： XE88LC05AMI028
所含物品： 完全組裝的評估板
Semtech 2006
www.semtech.com
8-2
XE8805/05A
8.1
Features
The XE8000 chips support 24 interrupt sources, divided into 3 levels of priority.
8.2
Overview
A CPU interruption is generated and memorized when an interrupt becomes active. The 24 interrupt sources are
divided into 3 levels of priority: High (8 interrupt sources), Mid (8 interrupt sources), and Low (8 interrupt sources).
Those 3 levels of priority are directly mapped to those supported by the CoolRisc (IN0, IN1 and IN2; see
CoolRisc documentation for more information).
RegIrqHig, RegIrqMid, and RegIrqLow are 8-bit registers containing flags for the interrupt sources. Those flags
are set when the interrupt is enabled (i.e. if the corresponding bit in the registers RegIrqEnHig, RegIrqEnMid or
RegIrqEnLow is set) and a rising edge is detected on the corresponding interrupt source.
Once memorized, an interrupt flag can be cleared by writing a ‘1’ in the corresponding bit of RegIrqHig, RegIrqMid
or RegIrqLow. Writing a ‘0’ does not modify the flag. To definitively clear the interrupt, one has to clear the
CoolRisc interrupt in the CoolRisc status register. All interrupts are automatically cleared after a reset.
Two registers are provided to facilitate the writing of interrupt service software. RegIrqPriority contains the number
of the highest priority interrupt set (its value is 0xFF when no interrupt is set). RegIrqIrq indicates the priority level
of the current interrupts. RegIrqIrq and RegIrqPriority ‘s values are dependent upon the memorized state of the
interrupts (as reflected in flags in RegIrqHig, RegIrqMid and RegIrqLow).
8.3
Register map
pos.
RegIrqHig
rw
reset
function
7
RegIrqHig[7]
r
c1
0 resetsystem
interrupt #23 (high priority)
clear interrupt #23 when 1 is written
6
RegIrqHig[6]
r
c1
0 resetsystem
interrupt #22 (high priority)
clear interrupt #22 when 1 is written
5
RegIrqHig[5]
r
c1
0 resetsystem
interrupt #21 (high priority)
clear interrupt #21 when 1 is written
4
RegIrqHig[4]
r
c1
0 resetsystem
interrupt #20 (high priority)
clear interrupt #20 when 1 is written
3
RegIrqHig[3]
r
c1
0 resetsystem
interrupt #19 (high priority)
clear interrupt #19 when 1 is written
2
RegIrqHig[2]
r
c1
0 resetsystem
interrupt #18 (high priority)
clear interrupt #18 when 1 is written
1
RegIrqHig[1]
r
c1
0 resetsystem
interrupt #17 (high priority)
clear interrupt #17 when 1 is written
0
RegIrqHig[0]
r
c1
0 resetsystem
interrupt #16 (high priority)
clear interrupt #16 when 1 is written
Table 8-1: RegIrqHig
Not
Recommended
for
New
Designs
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