參數(shù)資料
型號： XE8000EV104
廠商： Semtech
文件頁數(shù)： 54/156頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR XE8805AMI028LF
標(biāo)準(zhǔn)包裝： 1
類型： MCU
適用于相關(guān)產(chǎn)品： XE88LC05AMI028
所含物品： 完全組裝的評估板
Semtech 2006
www.semtech.com
20-7
XE8805/05A
When in upcount mode, the counter will start incrementing from zero up to the target value which has been written
in the corresponding RegCntX register(s). When the counter content is equal to the target value, an interrupt is
generated at the next falling edge of counter clock. Then the counter is loaded again with the zero value at the next
rising edge of counter clock (Figure 20-2).
When in downcount mode, the counter will start decrementing from the initial load value which has been written in
the corresponding RegCntX register(s) down to the zero value. Once the counter content is equal to zero, an
interrupt is generated at the next falling edge of counter clock. Then the counter is loaded again with the load value
at the next rising edge of counter clock (Figure 20-2).
Be careful to select the counter mode (no capture, not PWM, specify cascaded or not and up or down counting
mode) before writing any target or load value to the RegCntX register(s). This ensures that the counter will start
from the correct initial value. When counters are cascaded, both counter registers must be written to ensure that
both cascaded counters will start from the correct initial values.
The stopping and consecutive starting of a counter in counter mode without a target or load value write operation in
between can generate an interrupt if this counter has been stopped at the zero value (downcount) or at it’s target
value (upcount). This interrupt is additional to the interrupt which has already been generated when the counter
reached the zero or the target value.
dow n counting
clock counter X
RegcntX_r
XX
3
21
032
103
210
RegCntX_w
XX
3
write RegCntX
CntXDownUp
IrqX
CntXEnable
up counting
clock counter X
RegCntX_r
XX
0
1
230
123
012
3
RegCntX_w
XX
3
write RegCntX
CntXDownUp
IrqX
CntXEnable
Figure 20-2. Up and down count interrupt generation.
Not
Recommended
for
New
Designs
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