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參數(shù)資料
| 型號(hào)： | XE8000EV104 |
| 廠商： | Semtech |
| 文件頁數(shù)： | 123/156頁 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR XE8805AMI028LF |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | XE88LC05AMI028 |
| 所含物品： | 完全組裝的評(píng)估板 |
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Semtech 2006
www.semtech.com
12-5
XE8805/05A
The frequency of the CPU clock depends on the selection of the CpuSel bit in the RegSysClock register (see
clock_gen_ff).
Pins PB[5] and PB[4] can be used for S1 and S0 of the USRT (see USRT documentation) when the UsrtEnable bit
is set in RegUsrtCtrl. The PB[5] and PB[4] then become open-drain. This overrides the values contained in
PBOpen(5:4), PBOut(5:4) and PBDir(5:4). If there is no external pull-up resistor on these pins, internal pull-ups
should be selected by setting PBPullup(5:4). When S0 is an output, the pin PB[4] takes the value of UsrtS0 in
RegUrstS0. When S1 is an output, the pin PB[5] takes the value of UsrtS1 in RegUrstS1.
Pins PB[6] and PB[7] can be used by the UART (see UART documentation). When UartEnTx in RegUartCtrl is set
to 1, PB[6] is used as output signal Tx. When UartEnRx in RegUartCtrl is set to 1, PB[7] is used as input signal
Rx. This overrides the values contained in PBOut(7:6) and PBDir(7:6).
12.7 Port B digital capabilities
12.7.1
Port B digital configuration
The direction of each bit within Port B (input only or input/output) can be individually set using the RegPBDir
register. If PBDir[x] = 1, both the input and output buffer are active on the corresponding Port B. If PBDir[x] = 0,
the corresponding Port B pin is an input only and the output buffer is in high impedance. After reset (resetpconf)
Port B is in input only mode (PBDir[x] are reset to 0).
The input values of Port B are available in RegPBIn (read only). Reading is always direct - there is no debounce
function in Port B. In case of possible noise on input signals, a software debouncer with polling or an external
hardware filter have to be realized. The input buffer is also active when the port is defined as output and allows to
read back the effective value on the pin.
Data stored in RegPBOut are output at Port B if PBDir[x] is 1. The default value after reset is low (0).
When a pin is in output mode (PBDir[x] is set to 1), the output can be a conventional CMOS (Push-Pull) or a N-
channel Open-drain, driving the output only low. By default, after reset (resetpconf) the PBOpen[x] in RegPBOpen
is cleared to 0 (push-pull). If PBOpen[x] in RegPBOpen is set to 1 then the internal P transistor in the output buffer
is electrically removed and the output can only be driven low (PBOut[x]=0). When PBOut[x]=1, the pin is high
Impedance. The internal pull-up or an external pull-up resistor can be used to drive the pin high.
Note: Because the P transistor actually exists (this is not a real Open-drain output) the pull-up range is limited to
VDD + 0.2V (avoid forward bias the P transistor / diode).
Each bit can be set individually for pull-up or not using register RegPBPullup. Input is pulled up when its
corresponding bit in this register is set to 1. Default status after (resetpconf) is 0, which means without pull up. To
limit power consumption, pull-up resistors are only enabled when the associated pin is either a digital input or an N-
channel open-drain output with the pad set to 1. In the other cases (push-pull output or open-drain output driven
low), the pull up resistors are disabled independent of the value in RegPBPullup.
After power-on reset, the Port B is configured as an input port without pull-up.
The input buffer is always active, except in analog mode. This means that the Port B input should be a valid digital
value at all times unless the pin is set in analog mode. Violating this rule may lead to higher power consumption.
Not
Recommended
for
New
Designs
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