參數(shù)資料
型號： XE8000EV104
廠商： Semtech
文件頁數(shù)： 122/156頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR XE8805AMI028LF
標準包裝： 1
類型： MCU
適用于相關(guān)產(chǎn)品： XE88LC05AMI028
所含物品： 完全組裝的評估板
Semtech 2006
www.semtech.com
12-4
XE8805/05A
if x is even, PBDir[x+1, x]
PBPullup[x]
PB[x] selection on
00
1
analog line 0
01
1
analog line 1
10
1
analog line 2
11
1
analog line 3
XX
0
High impedance
Table 12-9: Selection of the analog lines for PB[x] when x is even and PBAna[x] = 1
Example:
Set the pads PB[2] and PB[3] on the analog line 3. (the values X depend on the configuration of others
pads)
-
apply high impedance in the analog mode (move RegPBPullup,#0bXXXX00XX)
-
go to analog mode (move RegPBAna,#0bXXXXXX1X)
-
select the analog line3 (move RegPBDir,#0bXXXX11XX and move RegPBOut,#0bXXXX11XX)
-
connect the analog line to the pins (move RegPBPullup,#0bXXXX11XX)
12.5.2
Port B analog function specification
The table below defines the on-resistance of the switches between the pin and the analog bus for different
conditions. The series resistance between 2 pins of Port B connected to the same analog line is twice the
resistance given in the table.
sym
description
min
typ
max
unit
Comments
Ron
switch resistance
11
k
Note 1
Ron
switch resistance
15
k
Note 2
Cin
input capacitance (off)
3.5
pF
Note 3
Cin
input capacitance (on)
4.5
pF
Note 4
Table 12-10. Analog input specifications.
Note 1: This is the series resistance between the pad and the analog line in 2 cases
1. VBAT
≥ 2.4V and the VMULT peripheral is present on the circuit and enabled.
2. VBAT
≥ 3.0V and the VMULT peripheral is not present on the circuit.
Note 2: This is the series resistance in case VBAT
≥ 2.8V and the peripheral VMULT is not present on the circuit.
Note 3: This is the input capacitance seen on the pin when the pin is not connected to an analog line. This value is
indicative only since it is product and package dependent.
Note 4: This is the input capacitance seen on the pin when the pin is connected to an analog line and no other pin
is connected to the same analog line. This value is indicative only since it is product and package dependent.
12.6 Port B function capability
The Port B can be used for different functions implemented by other peripherals. The description below is
applicable only in so far the circuit contains these peripherals.
When the counters are used to implement a PWM function (see the documentation of the counters), the PB[0] and
PB[1] terminals are used as outputs (PB[0] is used if CntPWM0 in RegCntConfig1 is set to 1, PB[1] is used if
CntPWM1 in RegCntConfig1 is set to 1) and the PWM generated values overwrite the values written in
RegPBout. However, PBDir(0) and PBDir(1) are not automatically overwritten and have to be set to 1.
If OutputCkXtal is set in RegSysMisc, the Xtal clock is output on PB[3] (EnableXtal in RegSysClock must be set
to 1). This overrides the value contained in PBOut(3). However, PBDir(3) must be set to 1. The duty cycle of the
clock signal is about 50%.
Similarly, if OutputCkCpu is set in RegSysMisc, the CPU frequency is output on PB[2]. This overrides the value
contained in PBOut(2). However, PBDir(2) must be set to 1.
Not
Recommended
for
New
Designs
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