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參數(shù)資料
| 型號(hào)： | XC3S1400AN-5FGG484C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 94/123頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SPARTAN-3AN 484FPGA |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | Spartan®-3AN |
| LAB/CLB數(shù)： | 2816 |
| 邏輯元件/單元數(shù)： | 25344 |
| RAM 位總計(jì)： | 589824 |
| 輸入/輸出數(shù)： | 372 |
| 門數(shù)： | 1400000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 484-BBGA |
| 供應(yīng)商設(shè)備封裝： | 484-FBGA |
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Spartan-3AN FPGA Family: Pinout Descriptions
DS557 (v4.1) April 1, 2011
Product Specification
72
Package Pins by Type
Each package has three separate voltage supply inputs—VCCINT, VCCAUX, and VCCO—and a common ground return,
GND. The numbers of pins dedicated to these functions vary by package, as shown in Table 63.
A majority of package pins are user-defined I/O or input pins. However, the numbers and characteristics of these I/Os
depend on the device type and the package in which it is available, as shown in Table 64. The table shows the maximum
number of single-ended I/O pins available, assuming that all I/O-, INPUT-, DUAL-, VREF-, and CLK-type pins are used as
general-purpose I/O. AWAKE is counted here as a dual-purpose I/O pin. Likewise, the table shows the maximum number of
differential pin-pairs available on the package. Finally, the table shows how the total maximum user-I/Os are distributed by
pin type, including the number of unconnected—N.C.—pins on the device.
Not all I/O standards are supported on all I/O banks. The left and right banks (I/O banks 1 and 3) support higher output drive
current than the top and bottom banks (I/O banks 0 and 2). Similarly, true differential output standards, such as LVDS,
RSDS, PPDS, miniLVDS, and TMDS, are only supported in the top or bottom banks (I/O banks 0 and 2). Inputs are
unrestricted. For more details, see the “Using I/O Resources” chapter in UG331.
CONFIG
Dedicated configuration pin, two per device. Not available as a user-I/O pin. Every package has
two dedicated configuration pins. These pins are powered by VCCAUX. See UG332: Spartan-3
Generation Configuration User Guide for additional information on the DONE and PROG_B
signals.
DONE, PROG_B
PWR
MGMT
Control and status pins for the power-saving Suspend mode. SUSPEND is a dedicated pin and
is powered by VCCAUX. AWAKE is a dual-purpose pin. Unless Suspend mode is enabled in the
application, AWAKE is available as a user-I/O pin.
SUSPEND, AWAKE
JTAG
Dedicated JTAG pin - 4 per device. Not available as a user-I/O pin. Every package has four
dedicated JTAG pins. These pins are powered by VCCAUX.
TDI, TMS, TCK, TDO
GND
Dedicated ground pin. The number of GND pins depends on the package used. All must be
connected.
GND
VCCAUX
Dedicated auxiliary power supply pin. The number of VCCAUX pins depends on the package
used. The In-System Flash memory is powered by VCCAUX. All must be connected to +3.3V.
VCCAUX
VCCINT
Dedicated internal core logic power supply pin. The number of VCCINT pins depends on the
package used. All must be connected to +1.2V.
VCCINT
VCCO
Along with all the other VCCO pins in the same bank, this pin supplies power to the output buffers
within the I/O bank and sets the input threshold voltage for some I/O standards. All must be
connected.
VCCO_#
N.C.
This package pin is not connected in this specific device/package combination.
N.C.
Notes:
1.
# = I/O bank number, an integer between 0 and 3.
Table 62: Types of Pins on Spartan-3AN FPGAs (Cont’d)
Type with
Color Code
Description
Pin Name(s) in
Type(1)
Table 63: Power and Ground Supply Pins by Package
Package
VCCINT
VCCAUX
VCCO
GND
TQG144
4
8
13
FTG256
6
4
16
28
FGG400
9
8
22
43
FGG484
15
10
24
53
FGG676
23
14
36
77
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| XC3S1400AN-5FGG676C | 功能描述:IC FPGA SPARTAN -3N1400K 676FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3AN 標(biāo)準(zhǔn)包裝:60 系列:XP LAB/CLB數(shù):- 邏輯元件/單元數(shù):10000 RAM 位總計(jì):221184 輸入/輸出數(shù):244 門數(shù):- 電源電壓:1.71 V ~ 3.465 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應(yīng)商設(shè)備封裝:388-FPBGA（23x23） 其它名稱:220-1241 |
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