參數(shù)資料
型號: XC3S1400AN-5FGG484C
廠商: Xilinx Inc
文件頁數(shù): 39/123頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN-3AN 484FPGA
標準包裝: 60
系列: Spartan®-3AN
LAB/CLB數(shù): 2816
邏輯元件/單元數(shù): 25344
RAM 位總計: 589824
輸入/輸出數(shù): 372
門數(shù): 1400000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 484-BBGA
供應商設備封裝: 484-FBGA
Spartan-3AN FPGA Family: DC and Switching Characteristics
DS557 (v4.1) April 1, 2011
Product Specification
22
External Termination Requirements for Differential I/O
LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards
BLVDS_25 I/O Standard
TMDS_33 I/O Standard
X-Ref Target - Figure 8
Figure 8: External Input Termination for LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards
X-Ref Target - Figure 9
Figure 9: External Output and Input Termination Resistors for BLVDS_25 I/O Standard
100
Ω
DS529-3_09_080307
a) Input-only Differential Pairs or Pairs not Using DIFF_TERM=Yes Constraint
Z0 = 50Ω
b) Differential Pairs Using DIFF_TERM=Yes Constraint
DIFF_TERM=No
DIFF_TERM=Yes
LVDS_33,
MINI_LVDS_33,
RSDS_33,
PPDS_33
LVDS_33, LVDS_25,
MINI_LVDS_33,
MINI_LVDS_25,
RSDS_33, RSDS_25,
PPDS_33, PPDS_25
CAT16-PT4F4
Part Number
1/4th of Bourns
VCCO = 3.3V
LVDS_25,
MINI_LVDS_25,
RSDS_25,
PPDS_25
VCCO = 2.5V
LVDS_33,
MINI_LVDS_33,
RSDS_33,
PPDS_33
VCCO = 3.3V
LVDS_25,
MINI_LVDS_25,
RSDS_25,
PPDS_25
VCCO = 2.5V
No VCCO Restrictions
R
LVDS_33,
MINI_LVDS_33,
RSDS_33,
PPDS_33
VCCO = 3.3V
LVDS_25,
MINI_LVDS_25,
RSDS_25,
PPDS_25
VCCO = 2.5V
DT
Bank 0
Bank 2
Bank 0
Bank 2
Ba
n
k
3
Ba
n
k
1
Bank 0 and 2
Any Bank
140
Ω
165
Ω
165
Ω
100
Ω
VCCO = 2.5V
No VCCO Requirement
DS529-3_07_080307
BLVDS_25
CAT16-LV4F12
Part Number
CAT16-PT4F4
Part Number
1/4th of Bourns
Bank 0
Bank 2
Ba
n
k
3
Ba
n
k
1
Any Bank
Bank 0
Bank 2
Ba
n
k
3
Ba
n
k
1
Any Bank
Z0 = 50Ω
X-Ref Target - Figure 10
Figure 10: External Input Resistors Required for TMDS_33 I/O Standard
50
Ω
VCCO = 3.3V
VCCAUX = 3.3V
DS529-3_08_020107
DVI/HDMI cable
50
Ω
3.3V
TMDS_33
Bank 0
Bank 2
Bank 0 and 2
Bank 0
Bank 2
B
a
nk
3
B
a
nk
1
Any Bank
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