參數(shù)資料
型號： XC3S1400AN-5FGG484C
廠商： Xilinx Inc
文件頁數(shù)： 76/123頁
文件大?。?/td> 0K
描述： IC FPGA SPARTAN-3AN 484FPGA
標準包裝： 60
系列： Spartan®-3AN
LAB/CLB數(shù)： 2816
邏輯元件/單元數(shù)： 25344
RAM 位總計： 589824
輸入/輸出數(shù)： 372
門數(shù)： 1400000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 484-BBGA
供應商設備封裝： 484-FBGA
Spartan-3AN FPGA Family: DC and Switching Characteristics
DS557 (v4.1) April 1, 2011
Product Specification
56
Phase Shifter (PS)
Miscellaneous DCM Timing
Table 43: Recommended Operating Conditions for the PS in Variable Phase Mode
Symbol
Description
Speed Grade
Units
-5
-4
Min
Max
Min
Max
Operating Frequency Ranges
PSCLK_FREQ (FPSCLK) Frequency for the PSCLK input
1
167
1
167
MHz
Input Pulse Requirements
PSCLK_PULSE
PSCLK pulse width as a percentage of the PSCLK period
40%
60%
40%
60%
%
Table 44: Switching Characteristics for the PS in Variable Phase Mode
Symbol
Description
Phase Shift Amount
Units
Phase Shifting Range
MAX_STEPS(2,3)
Maximum allowed number of
DCM_DELAY_STEP steps for a given
CLKIN clock period, where T = CLKIN
clock period in ns. If using
CLKIN_DIVIDE_BY_2 = TRUE, double
the clock effective clock period.
CLKIN < 60 MHz
[INTEGER(10 (T
CLKIN – 3 ns))]
steps
CLKIN
60 MHz [INTEGER(15 (T
CLKIN – 3 ns))]
FINE_SHIFT_RANGE_MIN
Minimum guaranteed delay for variable phase shifting
[MAX_STEPS
DCM_DELAY_STEP_MIN]
ns
FINE_SHIFT_RANGE_MAX
Maximum guaranteed delay for variable phase shifting
[MAX_STEPS
DCM_DELAY_STEP_MAX]
ns
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 10 and Table 43.
2.
The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, that is, the
PHASE_SHIFT attribute is set to 0.
3.
The DCM_DELAY_STEP values are provided at the bottom of Table 40.
Table 45: Miscellaneous DCM Timing
Symbol
Description
Min
Max
Units
DCM_RST_PW_MIN
Minimum duration of a RST pulse width
3
–CLKIN
cycles
DCM_RST_PW_MAX(2)
Maximum duration of a RST pulse width
N/A
seconds
N/A
seconds
DCM_CONFIG_LAG_TIME(3)
Maximum duration from VCCINT applied to FPGA configuration
successfully completed (DONE pin goes High) and clocks
applied to DCM DLL
N/A
minutes
N/A
minutes
Notes:
1.
This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV).
The DCM DFS outputs (CLKFX, CLKFX180) are unaffected.
2.
This specification is equivalent to the Virtex
-4 FPGA DCM_RESET specification. This specification does not apply for Spartan-3AN
FPGAs.
3.
This specification is equivalent to the Virtex-4 FPGA TCONFIG specification. This specification does not apply for Spartan-3AN FPGAs.
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