參數(shù)資料
型號(hào)： XC3S1400AN-5FGG484C
廠商： Xilinx Inc
文件頁數(shù)： 81/123頁
文件大小： 0K
描述： IC FPGA SPARTAN-3AN 484FPGA
標(biāo)準(zhǔn)包裝： 60
系列： Spartan®-3AN
LAB/CLB數(shù)： 2816
邏輯元件/單元數(shù)： 25344
RAM 位總計(jì)： 589824
輸入/輸出數(shù)： 372
門數(shù)： 1400000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 484-BBGA
供應(yīng)商設(shè)備封裝： 484-FBGA
Spartan-3AN FPGA Family: DC and Switching Characteristics
DS557 (v4.1) April 1, 2011
Product Specification
60
Configuration and JTAG Timing
General Configuration Power-On/Reconfigure Timing
X-Ref Target - Figure 13
Figure 13: Waveforms for Power-On and the Beginning of Configuration
Table 50: Power-On Timing and the Beginning of Configuration
Symbol
Description
Device
All Speed Grades
Units
Min
Max
TPOR(2)
The time from the application of VCCINT, VCCAUX, and VCCO
Bank 2 supply voltage ramps (whichever occurs last) to the
rising transition of the INIT_B pin
All
–18
ms
TPROG
The width of the low-going pulse on the PROG_B pin
All
0.5
–s
TPL(2)
The time from the rising edge of the PROG_B pin to the
rising transition on the INIT_B pin
XC3S50AN
–0.5
ms
XC3S200AN
–0.5
ms
XC3S400AN
–1
ms
XC3S700AN
–2
ms
XC3S1400AN
–2
ms
TINIT
Minimum Low pulse width on INIT_B output
All
250
–ns
TICCK(3)
The time from the rising edge of the INIT_B pin to the
generation of the configuration clock signal at the CCLK
output pin
All
0.5
4
s
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 10. This means power must be applied to all VCCINT, VCCO,
and VCCAUX lines.
2.
Power-on reset and the clearing of configuration memory occurs during this period.
3.
This specification applies only to the Master Serial, SPI, and BPI modes.
4.
For details on configuration, see UG332 Spartan-3 Generation Configuration User Guide.
VCCINT
(Supply)
VCCAUX
VCCO Bank 2
PROG_B
(Output)
(Open-Drain)
(Input)
INIT_B
CCLK
DS557-3_01_052908
1.2V
T
ICCK
T
PROG
T
PL
T
POR
1.0V
2.0V
3.3V
2.5V
or
Notes:
1.
When configuring from the In-System Flash, VCCAUX must be in the recommended operating range; on power-up make
sure VCCAUX reaches at least 3.0V before INIT_B goes High to indicate the start of configuration. VCCINT, VCCAUX, and
VCCO supplies to the FPGA can be applied in any order if this requirement is met.
2.
The Low-going pulse on PROG_B is optional after power-on but necessary for reconfiguration without a power cycle.
3.
The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).
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