參數(shù)資料
型號： XC3S1400AN-5FGG484C
廠商： Xilinx Inc
文件頁數(shù)： 101/123頁
文件大小： 0K
描述： IC FPGA SPARTAN-3AN 484FPGA
標(biāo)準(zhǔn)包裝： 60
系列： Spartan®-3AN
LAB/CLB數(shù)： 2816
邏輯元件/單元數(shù)： 25344
RAM 位總計： 589824
輸入/輸出數(shù)： 372
門數(shù)： 1400000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 484-BBGA
供應(yīng)商設(shè)備封裝： 484-FBGA
Spartan-3AN FPGA Family: Pinout Descriptions
DS557 (v4.1) April 1, 2011
Product Specification
79
FTG256: 256-Ball Fine-Pitch, Thin Ball Grid Array
The 256-ball fine-pitch, thin ball grid array package, FTG256, supports the XC3S50AN, XC3S200AN, and XC3S400AN
devices. Table 70 lists all the package pins for these devices. They are sorted by bank number and then by the pin name of
the largest device. Pins that form a differential I/O pair appear together in the table. The differential I/O pairs that have
different assignments between the XC3S50AN and the XC3S200AN or XC3S400AN are highlighted in light blue in Table 70.
See Footprint Migration Differences, page 87 for additional information. The table also shows the pin number for each pin
and the pin type (as defined in Table 62).
The footprints for the XC3S200AN and XC3S400AN in the FTG256 are identical. Figure 21 shows the common footprint for
the XC3S200AN and XC3S400AN. The XC3S50AN footprint is compatible with the XC3S200AN and XC3S400AN,
however, there are 51 unconnected balls (indicated as N.C. in Table 70).
Table 73 summarizes the XC3S50AN FPGA footprint migration differences for the FTG256 package.
The XC3S50AN does not support the address output pins for the byte-wide peripheral interface (BPI) configuration mode.
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at:
Pinout Table
Table 70: Spartan-3AN FTG256 Pinout (XC3S50AN, XC3S200AN, XC3S400AN)
Bank
XC3S50AN Pin Name
XC3S200AN/XC3S400AN Pin Name
FTG256 Ball
Type
0
IO_L01N_0
C13
I/O
0
IO_L01P_0
D13
I/O
0
IO_L02N_0
B14
I/O
0
IO_L02P_0/VREF_0
B15
VREF
0
IO_L03N_0
D11
I/O
0
IO_L03P_0
C12
I/O
0
IO_L04N_0
A13
I/O
0
IO_L04P_0
A14
I/O
0
N.C.
IO_L05N_0
A12
I/O
0
IP_0
IO_L05P_0
B12
I/O
0
N.C.
IO_L06N_0/VREF_0
E10
VREF
0
N.C.
IO_L06P_0
D10
I/O
0
IO_L07N_0
A11
I/O
0
IO_L07P_0
C11
I/O
0
IO_L08N_0
A10
I/O
0
IO_L08P_0
B10
I/O
0
IO_L09N_0/GCLK5
D9
GCLK
0
IO_L09P_0/GCLK4
C10
GCLK
0
IO_L10N_0/GCLK7
A9
GCLK
0
IO_L10P_0/GCLK6
C9
GCLK
0
IO_L11N_0/GCLK9
D8
GCLK
0
IO_L11P_0/GCLK8
C8
GCLK
0
IO_L12N_0/GCLK11
B8
GCLK
0
IO_L12P_0/GCLK10
A8
GCLK
0
N.C.
IO_L13N_0
C7
I/O
0
N.C.
IO_L13P_0
A7
I/O
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