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參數(shù)資料
| 型號： | W9412G6CH-5 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 DDR DRAM, 0.7 ns, PDSO66 |
| 封裝： | 0.400 INCH, 0.65 MM PITCH, ROHS COMPLIANT, TSOP2-66 |
| 文件頁數(shù)： | 53/55頁 |
| 文件大?。?/td> | 2011K |
| 代理商： | W9412G6CH-5 |
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W9412G6CH
Publication Release Date: Nov. 19, 2007
- 7 -
Revision A07
5. PIN DESCRIPTION
PIN NUMBER
PIN
NAME
FUNCTION
DESCRIPTION
28
32,
35
41
A0
A11
Address
Multiplexed pins for row and column address.
Row address: A0
A11.
Column address: A0
A8. (A10 is used for Auto-precharge)
26, 27
BS0, BS1
Bank Select
Select bank to activate during row address latch time, or
bank to read/write during column address latch time.
2, 4, 5, 7, 8, 10,
11, 13, 54, 56, 57,
59, 60, 62, 63, 65
DQ0
DQ15
Data Input/ Output
The DQ0 – DQ15 input and output data are synchronized
with both edges of DQS.
16,51
LDQS,
UDQS
Data Strobe
DQS is Bi-directional signal. DQS is input signal during write
operation and output signal during read operation. It is Edge-
aligned with read data, Center-aligned with write data.
24
CS
Chip Select
Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and previous
operation continues.
23, 22, 21
RAS ,
CAS
, WE
Command Inputs Command inputs (along with CS ) define the command
being entered.
20, 47
LDM, UDM
Write Mask
When DM is asserted “high” in burst write, the input data is
masked. DM is synchronized with both edges of DQS.
45, 46
CLK,
CLK
Differential Clock
Inputs
All address and control input signals are sampled on the
crossing of the positive edge of CLK and negative edge of
CLK
.
44
CKE
Clock Enable
CKE controls the clock activation and deactivation. When
CKE is low, Power Down mode, Suspend mode, or Self
Refresh mode is entered.
49
VREF
Reference Voltage VREF is reference voltage for inputs.
1, 18, 33
VDD
Power (+2.5V)
Power for logic circuit inside DDR SDRAM.
34, 48, 66
VSS
Ground
Ground for logic circuit inside DDR SDRAM.
3, 9, 15, 55, 61
VDDQ
Power (+2.5V) for
I/O Buffer
Separated power from VDD, used for output buffer, to
improve noise.
6, 12, 52, 58, 64
VSSQ
Ground for I/O
Buffer
Separated ground from VSS, used for output buffer, to
improve noise.
14, 17, 19, 25,
42, 43, 50, 53
NC1
No Connection
No connection
(NC pin should be connected to GND or
floating)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W9412G6IH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:2M × 4 BANKS × 16 BITS DDR SDRAM |
| W9412G6IH-5 | 功能描述:IC DDR-400 SDRAM 128MB 66TSSOPII RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-MFP 包裝:帶卷 (TR) |
| W9412G6JH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:2M ? 4 BANKS ? 16 BITS DDR SDRAM |
| W9412G6JH-4 | 制造商:Winbond Electronics Corp 功能描述:8*16B DDR1 制造商:Winbond Electronics Corp 功能描述:IC DDR SDRAM 128M 250MHZ 66TSOP |
| W9412G6JH-5 | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR SDRAM 128M-Bit 8Mx16 2.5V 66-Pin TSOP 制造商:Winbond Electronics Corp 功能描述:128M BIT DDR1 |
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