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參數(shù)資料
| 型號： | W9412G6CH-5 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 DDR DRAM, 0.7 ns, PDSO66 |
| 封裝： | 0.400 INCH, 0.65 MM PITCH, ROHS COMPLIANT, TSOP2-66 |
| 文件頁數(shù)： | 34/55頁 |
| 文件大?。?/td> | 2011K |
| 代理商： | W9412G6CH-5 |
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W9412G6CH
Publication Release Date:Nov. 19, 2007
- 4 -
Revision A07
1. GENERAL DESCRIPTION
W9412G6CH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR
SDRAM); organized as 2M words
× 4 banks × 16 bits. Using pipelined architecture and 0.11m
process technology, W9412G6CH delivers a data bandwidth of up to 444M words per second (-45).
To fully comply with the personal computer industrial standard, W9412G6CH is sorted into four speed
grades: -45, -5, -6 and -75 .The -45 is compliant to the DDR444/CL3 specification, the -5 is compliant
to the DDR400/CL3 specification, the -6 is compliant to the DDR333/CL2.5 specification and the -75 is
compliant to the DDR266/CL2 specification.
All Input reference to the positive edge of CLK (except for DQ, DM and CKE). The timing reference
point for the differential clock is when the CLK and CLK signals cross during a transition. Write and
Read data are synschronized with the both edges of DQS (Data Strobe).
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9412G6CH is ideal for main memory in
high performance applications.
2. FEATURES
2.5V
±0.2V Power Supply for DDR266
2.5V
±0.2V Power Supply for DDR333
2.6V
± 5% Power Supply for DDR400
2.6V
± 5% Power Supply for DDR444
Up to 222 MHz Clock Frequency
Double Data Rate architecture; two data transfers per clock cycle
Differential clock inputs (CLK and CLK )
DQS is edge-aligned with data for Read; center-aligned with data for Write
CAS Latency: 2, 2.5 and 3
Burst Length: 2, 4 and 8
Auto Refresh and Self Refresh
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = 1
15.6S Refresh interval (4K / 64 mS Refresh)
Maximum burst refresh cycle: 8
Interface: SSTL_2
Packaged in TSOP II 66-pin, 400 mil, 0.65 mm pin pitch, using Pb free with RoHS compliant
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| W942504CH-7 | 64M X 4 DDR DRAM, 0.75 ns, PDSO66 |
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| WA-A325CBM | Peripheral Interface |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W9412G6IH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:2M × 4 BANKS × 16 BITS DDR SDRAM |
| W9412G6IH-5 | 功能描述:IC DDR-400 SDRAM 128MB 66TSSOPII RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-MFP 包裝:帶卷 (TR) |
| W9412G6JH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:2M ? 4 BANKS ? 16 BITS DDR SDRAM |
| W9412G6JH-4 | 制造商:Winbond Electronics Corp 功能描述:8*16B DDR1 制造商:Winbond Electronics Corp 功能描述:IC DDR SDRAM 128M 250MHZ 66TSOP |
| W9412G6JH-5 | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR SDRAM 128M-Bit 8Mx16 2.5V 66-Pin TSOP 制造商:Winbond Electronics Corp 功能描述:128M BIT DDR1 |
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