參數(shù)資料
型號: W9412G6CH-5
廠商: WINBOND ELECTRONICS CORP
元件分類: DRAM
英文描述: 8M X 16 DDR DRAM, 0.7 ns, PDSO66
封裝: 0.400 INCH, 0.65 MM PITCH, ROHS COMPLIANT, TSOP2-66
文件頁數(shù): 36/55頁
文件大小: 2011K
代理商: W9412G6CH-5
W9412G6CH
Publication Release Date: Nov. 19, 2007
- 41 -
Revision A07
11.6 Mode Register Set (MRS) Timing
MRS
Register Set data
NEXT CMD
tMRD
CLK
CMD
ADD
A2
A1
A0
A3
A6
A5
A4
A8
BS1
BS0
00
0
00
0
00
1
01
0
01
1
10
0
10
1
11
0
11
1
00
1
01
0
01
1
10
0
10
1
11
0
11
1
0
1
0
1
0
1
0
1
2
4
8
2
4
8
Burst Length
Sequential
Interleaved
Reserved
Sequential
Interleaved
Addressing Mode
CAS Latency
2
DLL Reset
No
Yes
MRS or EMRS
Regular MRS cycle
Extended MRS cycle
2.5
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
BS0
BS1
"0"
DLL Reset
Reserved
Addressing Mode
* "Reserved" should stay "0" during MRS cycle.
Reserved
Mode Register Set
or
Extended Mode
Register Set
CAS Latency
Burst Length
Reserved
3
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